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E1M-AEN Datasheet

E1M-AEN module — frontE1M-AEN module — back
E1M-AEN module — front (left) and back (right)

The E1M-AEN Ensemble series modules use the open-source Edge-1 AI Module (E1M™) form factor, with a unified pin layout and hardware functionality. This footprint allows users to interchange MCU/MPU modules seamlessly while keeping hardware compatible. E1M™ is designed for flexibility, functionality, and longevity in high- and medium-range MCU/MPUs.

Features​

  • Various core options with the same footprint, based on the Alif Semi Ensemble MCU/MPU series:
    • E8 — 2 × 800 MHz ARM A32, 2 × ARM M55, 2 × ARM Ethos U55 + 1 × ARM Ethos U85
    • E7 — 2 × 800 MHz ARM A32, 2 × ARM M55, 2 × ARM Ethos U55
    • E6 — 1 × 800 MHz ARM A32, 2 × ARM M55, 2 × ARM Ethos U55 + 1 × ARM Ethos U85
    • E5 — 1 × 800 MHz ARM A32, 2 × ARM M55, 2 × ARM Ethos U55
    • E4 — 2 × ARM M55, 2 × ARM Ethos U55 + 1 × ARM Ethos U85
    • E3 — 2 × ARM M55, 2 × ARM Ethos U55
  • Internal memory: 128 KB – 13.5 MB SRAM on-die, 256 KB – 5.5 MB MRAM
  • External memory: up to 2 × OSPI (configurable RAM or ROM)
  • MIPI DSI display output, 2 lanes, up to FHD
  • MIPI CSI-2 camera input, 2 lanes
  • Dual-band (2.4 GHz / 5 GHz) Wi-Fi 6 with up to 20 Mbps throughput
  • Bluetooth LE 5.4
  • 100 Mbps Ethernet PHY
  • CAN-BUS PHY
  • Assembly variants available for cost reduction
  • Small size: 35 × 35 mm

Applications​

IoT, industrial, robotics, motor drive, drones, mobile PoS, smart speakers, object detection, medical devices, vending machines, smart home, process control, smart appliances, scanners.

General Description​

Highlights​

The Alp Lab E1M-AEN System-on-Module (SoM) is a low-power, cost-effective solution for edge-AI applications. Powered by the Alif Semiconductor Ensemble series processor, it features an Arm Cortex-A32 application CPU (up to 2 × 800 MHz), Arm Cortex-M55 real-time cores, integrated Arm Ethos U55 / U85 NPUs, and an optional JPEG encoder and ISP, making it suitable for low-power edge-AI tasks.

The E1M-AEN supports one camera over a 2-lane MIPI CSI-2 interface and provides customizable options including on-board Wi-Fi / Bluetooth, multiple memory and storage configurations, and PHY variants.

Block Diagram​

E1M-AEN Block Diagram

Module Variants​

The E1M-AEN family ships in six MPN variants that share a common E1M™ footprint. Variants differ in the Ensemble SoC used, the application-CPU (A32) count, and the on-die NPU/ISP configuration. See Ordering Information for the full ordering matrix and MPN decoder; the table below summarises the differences.

Table: E1M-AEN Variant Summary

MPNEnsembleA32 coresNPUsISP / JPEG
E1M-AEN301E3—2 × U55—
E1M-AEN501E51 × 800 MHz2 × U55—
E1M-AEN701E72 × 800 MHz2 × U55—
E1M-AEN401E4—2 × U55 + 1 × U85Yes
E1M-AEN601E61 × 800 MHz2 × U55 + 1 × U85Yes
E1M-AEN801E82 × 800 MHz2 × U55 + 1 × U85Yes

Alif Semi Ensemble MCUs/MPUs​

This document should be read together with the corresponding Alif Semiconductor Ensemble MCU/MPU datasheet.

Alif Semi Ensemble MCU/MPU Series

Table: Ensemble MPU Options

EnsembleMCUMPUNPUInternal MemoryExternal MemoryISP / JPEG
E32 × M55—2 × U555.5 MB – 13.5 MB2 × OSPI—
E52 × M551 × A32 800 MHz2 × U555.5 MB – 13.5 MB2 × OSPI—
E72 × M552 × A32 800 MHz2 × U555.5 MB – 13.5 MB2 × OSPI—
E42 × M55—2 × U55 + 1 × U855.5 MB – 9.75 MB2 × OSPIYes
E62 × M551 × A32 800 MHz2 × U55 + 1 × U855.5 MB – 9.75 MB2 × OSPIYes
E82 × M552 × A32 800 MHz2 × U55 + 1 × U855.5 MB – 9.75 MB2 × OSPIYes

Pin Diagram and List​

The E1M™ standard defines the primary pin functions; the pin-out below follows that standard. Pins can be reassigned to alternate functions in software, but hardware compatibility with other E1M variants will no longer hold because each MCU/MPU has a different pin structure and peripheral mapping.

E1M-AEN Pin-out (top view, 312-pad LGA)

Power & Control Pins​

Table: E1M-AEN Power & Control Pins

Pin NumberPin NameDescription
A1, A11, A17, A20, A30, A32, AA33, AA34, AC1, AC2, AC33, AC34, AE1, AE32, AF2, AF33, AF34, AG1, AG3, AG19, AG25, AH2, AH3, AH15, AH19, AH25, B11, B17, B20, B30, B32, D3, E2, G33, G34, H1, H2, K1, K2, M33, M34, Q1, Q2, S33, S34, T1, T2, Y33, Y34GNDGround.
R1, S1, R2, S2VDD+5V main supply input to the module.
P1, P2VIO_OUT+1V8 output for IO power, up to 200 mA.
Z34+V_CAM0Adjustable LDO output (TLV77201). 0.6 V to 3.3 V, 300 mA max. Camera rail or general-purpose carrier load.
AB34+V_CAM1Adjustable LDO output (TLV77201). 0.6 V to 3.3 V, 300 mA max. Camera rail or general-purpose carrier load.
Z33CAM_VFB0Feedback node for +V_CAM0. Set output voltage via external divider; place close to the module pin.
AB33CAM_VFB1Feedback node for +V_CAM1. Set output voltage via external divider; place close to the module pin.
AH10SD_VDDSD/eMMC card power output.
AG15+S_CAPNot available for Alif Ensemble series.
O1MODULE_ENModule enable. Open-drain. Pulled up internally to VDD. Connect to GND to disable the module; leave floating if not used.
O2MODULE_STBYModule stand-by. Pulled up internally to 1V8. On E1M-AEN, stand-by is supported only for the real-time clock. Leave floating if not used.
W1PORnReset input. Open-drain. Pulled up internally to 1V8. Pull low to reset the module; leave floating if not used.
U1BOOT2E1M boot-strap pins. Alif SoCs do not have boot-mode pins; not used on E1M-AEN. Leave floating.
U2BOOT1
V1BOOT3
V2BOOT0
X1JTAG_TCK/SWDCLKJTAG/SWD pins for programming and debug.
X2JTAG_TDI
Y1JTAG_TMS/SWDIO
Y2JTAG_TDO
Z1JTAG_nRST
AH1ANT_2.4GHZPrimary antenna feed (RF_ANT) from the on-module BDE-BW3551N. Route 50 Ω trace to the antenna or connector.
AF1ANT_5GHZSeparate 5 GHz feed. The BDE-BW3551N uses a single combined antenna port (ANT_2.4GHZ), so this pin is not used on E1M-AEN. Leave floating.
AD1ANT_6GHZ6 GHz antenna (Wi-Fi 6E). Not used on E1M-AEN. Leave floating.
A31BL_LED_ABacklight LED anode / BL_PWM. Connect to backlight driver.
B31BL_LED_KBacklight LED cathode. Leave floating if BL_PWM is used.

Analog Pins​

Table: E1M-AEN Analog Pins

Pin NumberPin NamePeripheralDescription
A12ANA_S6AINAnalog input channels, referenced to 1V8.
A13ANA_S4
A14ANA_S2
A15ANA_S0
B12ANA_S7
B13ANA_S5
B14ANA_S3
B15ANA_S1
A16DAC0DAC0Analog output channel, referenced to 1V8.
B16DAC1DAC1Analog output channel, referenced to 1V8.

Digital Pins​

Table: E1M-AEN Digital Pins

Pin NumberPin NamePeripheralDescription
A18IO11GPIOGeneral purpose input/output.
AG2IO3
AG16IO4
AG18IO6
AG33IO8
AG34IO7
AH18IO5
AH33IO10
AH34IO9
E3IO13
F3IO15
G3IO16
H3IO17
I3IO18
J3IO19
K3IO20
L2IO0
W2IO2
Z2AUDIO_CLK—Audio clock output.
AA1PDM_C0PDM0Digital microphone interface.
AA2PDM_D0
AB1PDM_C1PDM1Digital microphone interface.
AB2PDM_D1
AD33I2S0_SDII2S0I2S interface.
AD34I2S0_SDO
AE33I2S0_SCLK
AE34I2S0_WS
AG6I2S1_SDOI2S1I2S interface.
AG7I2S1_WS
AH6I2S1_SDI
AH7I2S1_SCLK
AD2I2C0_SDAI2C0I2C interface.
AE2I2C0_SCL
AG17I2C1_SCLI2C1I2C interface.
AH17I2C1_SDA
AG5I3C_SCLI3CI3C interface.
AH5I3C_SDA
L1SPI0_MISOSPI0SPI interface.
M1SPI0_CS0
M2SPI0_MOSI
N1SPI0_CS1
N2SPI0_SCLK
AG8SPI1_MISOSPI1SPI interface.
AG9SPI1_MOSI
AG10SPI1_SCLK
AH8SPI1_CS1
AH9SPI1_CS0
F2UART0_TXUART0UART interface.
G2UART0_RX
AG4UART1_TXUART1UART interface.
AH4UART1_RX
A19CAN_STBYCAN0CAN-BUS interface.
B18CAN0H/CAN0_TX
B19CAN0L/CAN0_RX
A3PWM6PWMPWM output.
A4PWM4
A5PWM2
A6PWM0
B3PWM7
B4PWM5
B5PWM3
B6PWM1
A10ENC0_XENC0Encoder input.
B10ENC0_Y
A9ENC1_XENC1Encoder input.
B9ENC1_Y
A8ENC2_XENC2Encoder input.
B8ENC2_Y
A7ENC3_XENC3Encoder input.
B7ENC3_Y
AG29ETH0_DB_PETH0Ethernet interface. 100 Mbit PHY connection.
AG30ETH0_DA_P
AG31ETH0_LED0
AH29ETH0_DB_N
AH30ETH0_DA_N
AH31ETH0_LED1
AG11SD_CLKSD0SD card or eMMC interface.
AG12SD_D0
AG13SD_D2
AG14SD_DET
AH11SD_CMD
AH12SD_RST
AH13SD_D1
AH14SD_D3
P33CSI0_C_PCSI0MIPI CSI-2 camera interface.
P34CSI0_C_N
Q33CSI0_1_P
Q34CSI0_1_N
R33CSI0_0_P
R34CSI0_0_N
D33DSI0_C_PDSI0MIPI DSI display interface.
D34DSI0_C_N
E33DSI0_1_P
E34DSI0_1_N
F33DSI0_0_P
F34DSI0_0_N
AA32CAM_D5CAM_PARParallel camera interface.
AB32CAM_D6
AC32CAM_D7
AD32CAM_D8
S32CAM_VSYNC
T32CAM_HSYNC
U32CAM_XVCLK
V32CAM_PCLK
W32CAM_D1
X32CAM_D2
Y32CAM_D3
Z32CAM_D4
I1USB2_PUSB0USB 2.0 interface (routed to the E1M standard USB2 pins).
J1USB2_N
I2USB2_VBUS
J2USB2_ID
AH16RTC_CLKOUT—Real-time clock output.
AD3DBG_TXDBGOn-module debug UART. Defaults to debug UART; selectable to GPIO.
AE3DBG_RX

Not Connected Pins​

These pins carry an E1M standard function that is not implemented on E1M-AEN. They retain their standard name for cross-variant compatibility and must be left floating.

Table: E1M-AEN Not-connected Pins

Pin NumberPin NameDescription
AG27ETH0_DD_PETH0 gigabit pairs (DC/DD) — E1M-AEN Ethernet is 100 Mbit. Leave floating.
AG28ETH0_DC_P
AH27ETH0_DD_N
AH28ETH0_DC_N
AG20ETH1_DD_PSecond Ethernet (ETH1) — not implemented on E1M-AEN. Leave floating.
AG21ETH1_DC_P
AG22ETH1_DB_P
AG23ETH1_DA_P
AG24ETH1_LED0
AH20ETH1_DD_N
AH21ETH1_DC_N
AH22ETH1_DB_N
AH23ETH1_DA_N
AH24ETH1_LED1
A21PCIE0_TX0_PPCI Express (PCIE0) — not implemented on E1M-AEN. Leave floating.
A22PCIE0_TX1_P
A23PCIE0_TX2_P
A24PCIE0_TX3_P
A25PCIE0_RX0_P
A26PCIE0_RX1_P
A27PCIE0_RX2_P
A28PCIE0_RX3_P
A29PCIE0_CLK_P
B21PCIE0_TX0_N
B22PCIE0_TX1_N
B23PCIE0_TX2_N
B24PCIE0_TX3_N
B25PCIE0_RX0_N
B26PCIE0_RX1_N
B27PCIE0_RX2_N
B28PCIE0_RX3_N
B29PCIE0_CLK_N
B1USB0_30_D_PUSB0 port — not used on E1M-AEN; the USB 2.0 interface is routed to the USB2 pins. Leave floating.
C1USB0_30_D_N
C2USB0_VBUS
D2USB0_30_ID
A2USB_CC1USB SuperSpeed lanes and USB-C configuration — not used on E1M-AEN. Leave floating.
B2USB_CC2
D1USB0_30_RX0_P
E1USB0_30_RX0_N
F1USB0_30_TX0_P
G1USB0_30_TX0_N
B33DSI0_3_PMIPI DSI0 lanes 2 and 3 — E1M-AEN DSI is 2-lane. Leave floating.
B34DSI0_3_N
C33DSI0_2_P
C34DSI0_2_N
H33DSI1_3_PSecond MIPI DSI (DSI1) — not implemented on E1M-AEN. Leave floating.
H34DSI1_3_N
I33DSI1_2_P
I34DSI1_2_N
J33DSI1_C_P
J34DSI1_C_N
K33DSI1_1_P
K34DSI1_1_N
L33DSI1_0_P
L34DSI1_0_N
N33CSI0_3_PMIPI CSI0 lanes 2 and 3 — E1M-AEN CSI is 2-lane. Leave floating.
N34CSI0_3_N
O33CSI0_2_P
O34CSI0_2_N
T33CSI1_3_PSecond MIPI CSI (CSI1) — not implemented on E1M-AEN. Leave floating.
T34CSI1_3_N
U33CSI1_2_P
U34CSI1_2_N
V33CSI1_C_P
V34CSI1_C_N
W33CSI1_1_P
W34CSI1_1_N
X33CSI1_0_P
X34CSI1_0_N
L3IO21GPIO not bonded on E1M-AEN. Leave floating.
M3IO22
N3IO23
O3IO24
P3IO25

Reserved Pins​

Table: E1M-AEN Reserved Pins

Pin NumberPin NameDescription
A33, A34, AA3, AB3, AC3, AG26, AG32, AH26, AH32, D32, E32, F32, G32, H32, I32, J32, K32, L32, M32, N32, O32, P32, Q3, Q32, R3, R32, S3, T3, U3, V3, W3, X3, Y3, Z3RSVDDo not connect. Used for production purposes.

Specifications​

Absolute Maximum Ratings​

Warning: Stresses beyond Absolute Maximum Ratings may cause permanent damage. Operation at these conditions is not implied.

Table: E1M-AEN Absolute Maximum Ratings

ParameterSymbolMinMaxUnit
Power-supply voltageVDDIN to GND− 0.36.0V
Analog input voltageV(ANA_Sx)− 0.31.98V
Digital IO (1V8)− 0.31.98V
CAN bus voltage (CAN0H / CAN0L)V(CANx)− 58+58V
Ethernet MDI (TD±, RD±)V(MDI)− 0.3+4V
Backlight boost switch nodeV(LX)− 0.3+40V
Maximum junction temperatureTJ− 40+150°C

The module is specified to meet the Electrical Characteristics in Electrical Characteristics over the conditions below. Operation outside this range is not guaranteed.

Table: E1M-AEN Recommended Operating Conditions

ParameterSymbolMinTypMaxUnit
Module supply voltageVDDIN4.55.05.5V
Ambient operating temperature (S grade)TA− 40—+85°C
Ambient operating temperature (E grade)TA− 40—+105°C
Junction operating temperatureTJ− 40—+105°C
Relative humidity (operating, non-condensing)RHTBD—TBD%

Electrical Characteristics​

Table: E1M-AEN Electrical Characteristics

SymbolDescriptionMinNomMaxUnit
Power supply
IDDMAXMaximum IDD current——TBDmA
Analog inputs
V(AINx)Input voltage0—1.8V
Digital IOs (1.8 V LVCMOS)
VOLLow-level output voltage (at rated IOL)——0.4V
VOHHigh-level output voltage (at rated IOH)1.4——V
VILLow-level input voltage——0.63V
VIHHigh-level input voltage1.17——V
Adjustable LDO outputs (+V_CAM0 / +V_CAM1)
+V_CAM0Adjustable LDO output (TLV77201)0.6—3.3V
+V_CAM1Adjustable LDO output (TLV77201)0.6—3.3V

Note: Digital IO levels assume 1.8 V LVCMOS signalling (VIL ≤ 0.35·VDDIO, VIH ≥ 0.65·VDDIO). Confirm against the final Alif Ensemble SoC datasheet revision for the configured drive strength.

ESD & Latch-up Ratings​

ESD ratings apply at module-level — i.e. directly to the LGA pads as exposed to a carrier-board assembly process. The values below reflect the Ensemble SoC silicon ratings as seen at the LGA pads. With the exception of the SDIO / SD-card interface — which retains on-module ESD protection and series resistors — the module does not integrate interface ESD or EMI protection; the carrier board must provide external ESD/EMI protection on all exposed external-facing interfaces, as described in the relevant interface sub-sections. The HFXO / LFXO clock pins are not exposed on the module.

Table: E1M-AEN ESD & Latch-up Ratings

ParameterStandardMinMaxUnit
Human Body Model (HBM)ANSI/ESDA/JEDEC JS-001± 2000—V
Charged Device Model (CDM)ANSI/ESDA/JEDEC JS-002± 250—V
Latch-upJESD78± 100—mA

Thermal Characteristics​

The E1M-AEN dissipates heat primarily through the Ensemble SoC. The thermal-resistance figures below are the Ensemble SoC package values (FBGA194, junction-to-free-air in natural convection per the Alif datasheet); the realised module-level performance additionally depends on carrier-board copper area, airflow, and via stitching. Maximum junction temperature is the Ensemble SoC operating limit (absolute maximum +150 °C, see Absolute Maximum Ratings).

Table: E1M-AEN Thermal Characteristics

ParameterSymbolTypMaxUnit
Thermal resistance, junction-to-ambient (still air)θJA21.1—°C/W
Thermal resistance, junction-to-caseθJC17.0—°C/W
Maximum junction temperatureTJ,max—+105°C
Power dissipation derating (above +85 °C)PDTBD—mW/°C

Power-dissipation derating curve (figure pending)

Power​

Power Architecture​

All power rails on the module are generated and managed on-board from a single externally-supplied 5 V input on the VDDIN pads. On-module power management is performed by an integrated PMIC; no external sequencing is required.

The E1M-AEN includes all necessary decoupling capacitors. Additional decoupling capacitors on the carrier board may improve performance further.

The module exposes the following regulated output rails to the carrier:

Table: Module Output Rails

RailPinsVoltageMax currentPurpose
VIO_OUTP1, P21.8 V ± 5%200 mAI/O reference for carrier-side level shifters.
+V_CAM0Z340.6 – 3.3 V (adj.)300 mAAdjustable LDO (TLV77201), set via CAM_VFB0. Camera rail or general-purpose carrier load.
+V_CAM1AB340.6 – 3.3 V (adj.)300 mAAdjustable LDO (TLV77201), set via CAM_VFB1. Camera rail or general-purpose carrier load.

E1M-AEN Power Architecture Diagram (figure pending)

Power-Up & Reset Sequence​

The recommended power-up sequence is:

  1. Apply 5 V to VDDIN.
  2. Release MODULE_EN (let internal pull-up hold high).
  3. Release PORn (let internal pull-up hold high).
  4. Wait for the internal rails to stabilise and the SoC boot ROM to start. Power-up time is TBD ms.
  5. Begin communication with the module.

E1M-AEN Power-Up Timing (module level)

Note: For power-down, drive MODULE_EN low and remove VDDIN. The module does not require a controlled power-down sequence at the carrier-board level.

Power Consumption​

Numbers below are typical at TA = +25 °C, VDDIN = 5.0 V, with Wi-Fi and BLE disabled unless otherwise noted. Active and low-power figures depend on the Ensemble variant and software workload.

Table: E1M-AEN Power Consumption (typical)

ModeDescriptionMinTypMaxUnit
Active
Active, A32 + M55 + NPU @ full clockWorst-case AI inference—TBDTBDmA
Active, A32 idle / M55 runningReal-time only—TBDTBDmA
Active, with Wi-Fi 6 TX @ +20 dBmWireless TX peak—TBDTBDmA
Low-power
IdleCores halted, peripherals on—TBD—mA
SleepRetention only, RTC running—TBD—μA
Shutdown (MODULE_EN low)Module disabled—TBD—μA

Boot Modes​

Alif Semiconductor SoCs have no boot-mode strap pins; the boot flow is fixed and programmed into the internal ROM. The E1M BOOT0–BOOT3 strap pins defined in the E1M™ specification are therefore not used on E1M-AEN and should be left floating.

The boot ROM loads the application image from MRAM. External boot sources (OSPI flash, SD card) are selected in software once the boot ROM is running.

Note: Refer to the Alif Semiconductor Ensemble series boot reference manual for the internal boot sequence and image-signing requirements.

Reset & Module Enable​

The E1M-AEN exposes three carrier-controllable control signals:

Table: Reset & Module Enable Signals

PinDirectionDescription
MODULE_ENInput, open-drainInternally pulled up to VDDIN. Pull low to disable the module (forces shutdown). Leave floating if unused.
PORnInput, open-drainInternally pulled up to 1V8. Pull low to issue a power-on reset to the SoC. Minimum low-pulse width: TBD μs.
MODULE_STBYInput, open-drainInternally pulled up to 1V8. On E1M-AEN, stand-by is supported only for the real-time clock. Leave floating if unused.

E1M-AEN Reset Timing (PORn warm reset)

JTAG / SWD Debug​

The E1M-AEN exposes a 5-pin JTAG/SWD interface for programming and debug. Signals operate at 1.8 V; carrier-board level shifters are required for 3.3 V debug probes.

Table: JTAG / SWD Pinout

PinSignalDescription
Z1JTAG_nRSTActive-low reset to the SoC debug logic.
X1JTAG_TCK / SWDCLKTest clock (JTAG) or serial-wire clock (SWD).
X2JTAG_TDITest data in (JTAG only).
Y2JTAG_TDOTest data out (JTAG only).
Y1JTAG_TMS / SWDIOTest mode select (JTAG) or serial-wire I/O (SWD).

Note: Alp Lab recommends exposing the JTAG/SWD pins on a 10-pin Cortex-M debug header on the carrier board. Refer to the E1M Hardware Design Guide for the reference connector pinout.

Reference JTAG / SWD Header Pinout (figure pending)

Interfaces​

Ethernet​

E1M-AEN has one 100 Mbit Ethernet PHY: the TI DP83825I. The interface does not include on-module EMI or ESD protection; the user must provide an external magnetics transformer, connector, and EMI/ESD protection on the carrier board.

E1M-AEN Ethernet PHY Connection

The PHY is configured as follows:

Table: Ethernet PHY Configuration

FunctionSettingDescription
Auto-NegotiationEnabledAuto-Negotiation is enabled by default.
Auto MDI/MDIXEnabledAuto-MDIX is enabled by default.

Note: The DP83825I MDI pins (TD±, RD±) integrate ± 5 kV IEC 61000-4-2 ESD protection. External magnetics, connector, and additional EMI/ESD protection are still required on the carrier board.

USB​

E1M-AEN has one USB 2.0 interface. It supports Full-Speed (12 Mbit/s) and High-Speed (480 Mbit/s) bit rates and can operate as device or host.

Table: E1M-AEN USB Interface

Pin NumberPin NamePeripheralDescription
I1USB2_PUSB0Route USB2_P and USB2_N as a differential pair with 90 Ω impedance.
J1USB2_N
J2USB2_IDLow: Host mode. NC: Device mode.
I2USB2_VBUSConnect to USB VBUS 5 V.

Note: The USB 2.0 interface is brought out on the E1M standard USB2 pins (I1/J1). The USB0 pins (B1/C1/...), which carry the standard's optional USB 3.x SuperSpeed lanes, are not used on E1M-AEN and must be left floating.

Serial Interfaces​

I2C​

E1M-AEN exposes two I²C interfaces. Refer to the Alif Semiconductor Ensemble series datasheet for full details. External pull-ups are required.

I3C​

E1M-AEN exposes one I³C interface. Refer to the Alif Semiconductor Ensemble series datasheet for full details. External pull-ups are required.

UART​

E1M-AEN exposes two UART interfaces. Refer to the Alif Semiconductor Ensemble series datasheet for full details.

Note: One UART interface is connected to the secondary MCU on E1M. It is handled by the Alp SDK™ from the main MPU.

SPI​

E1M-AEN exposes two SPI interfaces. Refer to the Alif Semiconductor Ensemble series datasheet for full details.

Note: One SPI interface is connected to the secondary MCU on E1M. It is handled by the Alp SDK™ from the main MPU.

I2S​

E1M-AEN exposes two I²S interfaces. Refer to the Alif Semiconductor Ensemble series datasheet for full details.

CAN Bus​

E1M-AEN includes an optional CAN-BUS PHY (TI TCAN1044AVDRBRQ1) to simplify carrier-board hardware design. When the internal PHY is used, the user must add termination, ESD, and EMI protection components on the carrier board.

E1M-AEN CAN-BUS Connection

Note: The TCAN1044AVDRBRQ1 bus pins withstand ± 8 kV unpowered contact discharge and ± 15 kV air discharge per ISO 10605.

Wireless Module & Antenna​

E1M-AEN includes an on-board BDE-BW3551N dual-band (2.4 GHz / 5 GHz) Wi-Fi 6 and Bluetooth LE 5.4 combo module, based on the Texas Instruments SimpleLink™ CC3551E wireless MCU SoC. The module is backward-compatible with Wi-Fi 4 (802.11 a/b/g/n) and Wi-Fi 5 (802.11 ac). Its single-stream radio supports 20 MHz channels with application throughput up to 20 Mbps (UDP), and WPA / WPA2 / WPA3 personal and enterprise security. The module ANT output is brought out to the ANT pad (AH1) and may be routed to a U.FL connector or a carrier-board PCB antenna. Antenna selection is optional.

E1M-AEN Antenna Connection

RF Characteristics​

Table: E1M-AEN Wi-Fi 6 / BLE RF Characteristics

SymbolDescriptionMinTypMaxUnit
Wi-Fi 6 (802.11ax, 2.4 GHz)
fopOperating frequency range2412—2472MHz
PTXTX output power (HE MCS0)—18.2—dBm
PTXTX output power (HE MCS7)—15.7—dBm
PRXRX sensitivity (HE MCS0, 4K)—−89—dBm
PRXRX sensitivity (HE MCS7, 4K)—−70—dBm
Wi-Fi 6 (802.11ax, 5 GHz)
fopOperating frequency range5180—5845MHz
PTXTX output power (HE MCS0)—19.7—dBm
PTXTX output power (HE MCS7)—14.1—dBm
PRXRX sensitivity (HE MCS0, 4K)—−91.5—dBm
PRXRX sensitivity (HE MCS7, 4K)—−71.5—dBm
ηMax application throughput (UDP)—20—Mbps
Bluetooth LE 5.4
fopOperating frequency range2402—2480MHz
PTXTX output power (max setting)—16.3—dBm
PRXRX sensitivity (LE 1M, 37-byte)—−97.5—dBm
PRXRX sensitivity (LE Coded, 125 kbps)—−103.5—dBm

Note: Radio figures are BDE-BW3551N module specifications (typical, averaged across all channels). Values at the carrier-board antenna will be reduced by trace and connector losses.

Antenna Options​

The E1M-AEN antenna port can be routed three ways:

  1. On-module U.FL connector — connect an external antenna directly to the module.
  2. Carrier-board PCB antenna — route the ANT pad (AH1) out as a 50 Ω controlled-impedance trace to a chip or PCB antenna on the carrier board.
  3. Carrier-board RF connector — extend the 50 Ω trace to a U.FL / IPEX / SMA connector on the carrier board.

Maximum antenna gain to maintain regulatory compliance is TBD dBi.

Regulatory Information​

The on-module Wi-Fi 6 / BLE 5.4 combo is pre-certified for the regions listed below. Reusing the module's certifications on the customer's end product requires following the integration guidelines in the relevant certification reports.

Table: Wireless Regulatory Approvals

RegionStandardCertificate IDNotes
United StatesFCC Part 15TBDModular grant pending.
EuropeRED / CETBD—
CanadaISED RSS-247TBD—
JapanMIC (Japan)TBD—

Note: The on-module BDE-BW3551N wireless module is rated for ± 4 kV contact-discharge and ± 8 kV air-discharge ESD per EN 301-489. This is a module-level figure for the wireless subsystem; E1M-AEN pad-level HBM/CDM ratings are listed in the ESD & Latch-up Ratings table.

Warning: Certifications apply only when the module is used with the antenna(s) listed in the certification report. Using an unlisted antenna voids the modular grant and requires re-certification on the customer's end product.

SD Card​

E1M-AEN supports an external μSD card over the SDIO interface. The SDIO lines are protected on the module by an NXP NVT4858HKZ, which integrates an EMI filter and ESD protection, plus 33 Ω series resistors.

E1M-AEN SD Card Connection

Note: The NVT4858HKZ provides IEC 61000-4-2 level 4 ESD protection: ± 8 kV contact discharge and ± 15 kV air discharge.

MIPI DSI Display & Backlight Controller​

The Alif Ensemble series has a 2-lane MIPI DSI interface for an external display, supporting up to FHD resolution. The Ensemble series also includes a 2D GPU (D/AVE) that can accelerate display rendering.

E1M-AEN DSI Connection

E1M-AEN has a backlight driver (Kinetic KTD2801ECD-TR) for external screens, controlled directly from the Alp SDK™. The driver is optional; outputs are configured via the BL_LED_A and BL_LED_K pins. The driver supports up to 10 LEDs in series, or 2P6S, and integrates a 36 V over-voltage-protection (OVP) threshold on its boost switch node.

If the backlight driver is not needed, the BL_PWM signal can be exposed directly to drive an external backlight driver. The MIPI DSI interface does not include on-module EMI or ESD protection; protect the DSI lanes with a low-capacitance TVS array on the carrier board.

The feedback resistor value can be computed from the required LED current:

I_LED = 95 mV / R_FB

MIPI CSI Camera​

The Alif Ensemble series has a 2-lane MIPI CSI interface for an external camera. On the E4, E6, and E8 variants the Ensemble series also includes an internal JPEG encoder and ISP for accelerated image processing.

E1M-AEN CSI Connection

E1M supports direct camera implementation via on-board LDOs. Place the feedback resistors as close as possible to the CAM_VFBx pins. The MIPI CSI interface does not include on-module EMI or ESD protection; protect the CSI lanes with a low-capacitance TVS array on the carrier board.

The output voltage is set by the divider:

V_CAM = 0.6 V × (1 + R1 / R2)

To minimize feedback-pin current error, set the divider current to 100 × the maximum feedback-pin current. The resulting series resistance limit is:

R1 + R2 ≤ V_OUT / (I_FB × 100)

where I_FB,nom = 10 nA and I_FB,max = 100 nA.

Parallel Camera​

E1M-AEN provides an 8-bit parallel camera interface (CAM_PAR) for sensors that do not use MIPI CSI-2. The interface comprises the 8 data lines CAM_D1–CAM_D8, pixel clock CAM_PCLK, horizontal and vertical sync CAM_HSYNC / CAM_VSYNC, and the sensor master-clock output CAM_XVCLK. Sensor power can be supplied from the on-module adjustable LDO outputs (+V_CAM0 / +V_CAM1).

Microphone – PDM​

E1M supports up to 4 digital microphones over 2 PDM interfaces.

E1M-AEN PDM Connection

Refer to the E1M hardware design guide for full details.

Analog Inputs​

E1M provides 8 analog input channels. The Alif Ensemble series has a 12-bit ADC with a 5 Msps sampling rate. Analog inputs are referenced to 1V8.

An optional 0.1% standalone 1V8 reference is available on E1M.

Refer to the Alif Ensemble series datasheet for electrical characteristics.

Analog Outputs​

E1M provides 2 analog output channels. The Alif Ensemble series has a 12-bit DAC with a 1 kHz sampling rate. Analog outputs are referenced to 1V8.

Refer to the Alif Ensemble series datasheet for electrical characteristics.

Memories​

E1M-AEN offers several memory options. The Alif Ensemble series has internal ROM and RAM of up to 5.5 MB and 13.5 MB respectively.

Two optional OSPI memories are available on E1M-AEN; each can be configured as either RAM or ROM. A single OSPI interface is multiplexed across both memories. External memories are useful when running Linux or when additional RAM is required.

An optional I²C EEPROM is also available, connected through I²C0 on E1M. It can be flashed in production. I²C0 is also accessible on the E1M pinout. Refer to the E1M hardware design guide for details.

E1M-AEN Memory Options

Environmental & Reliability​

Operating & Storage Conditions​

Table: Environmental Conditions

ParameterSymbolMinMaxUnit
Ambient operating temperature (S grade)TA− 40+85°C
Ambient operating temperature (E grade)TA− 40+105°C
Storage temperatureTSTG− 40+125°C
Relative humidity (operating, non-condensing)RHTBDTBD%

Reflow Profile​

The E1M-AEN is qualified per IPC/JEDEC J-STD-020 to MSL TBD. The recommended lead-free reflow profile is shown in Reflow Profile, measured on a JTR1000 convection reflow oven using ALPHA OM338 (SAC, Pb-free) solder paste. Peak package temperature is 241–244 °C. Customers must follow the reflow profile below and the dry-pack handling instructions in MSL & Handling.

E1M-AEN Recommended Reflow Profile (Pb-free, SAC)

Table: Reflow Profile Parameters (Pb-free)

ParameterSymbolMinMaxUnit
Average ramp-up rate (TL to TP)——3°C/s
Preheat / soak time (150–217 °C)tS60120s
Time above liquidus (≥217 °C)tL4590s
Peak package temperatureTP241244°C
Average ramp-down rate (TP to TL)—− 1.6—°C/s
Time 25 °C to peak——8min

Reliability Data​

Table: Reliability Targets

ParameterSymbolValueUnit
Mean Time Between Failures (Telcordia SR-332, TA = +25 °C)MTBFTBDh
Moisture Sensitivity LevelMSLTBD—
Qualified shelf life (in dry-pack)—TBDmonths

Software & Operating System Support​

The E1M-AEN is supported by the open-source Alp SDK™, which provides a unified HAL across all E1M variants. Out of the box, the SDK supports:

  • Bare-metal application development on the Cortex-M55 real-time cores.
  • Zephyr RTOS on the Cortex-M55 cores (BSP e1m-aen upstream).
  • Linux on the Cortex-A32 application cores (E5/E6/E7/E8 variants), via Yocto/buildroot BSP. The E3/E4 variants are M55-only and do not support Linux.

Table: Software Support Matrix

VariantBare-metal (M55)Zephyr (M55)Linux (A32)
E1M-AEN301 (E3)YesYes—
E1M-AEN401 (E4)YesYes—
E1M-AEN501 (E5)YesYesYes
E1M-AEN601 (E6)YesYesYes
E1M-AEN701 (E7)YesYesYes
E1M-AEN801 (E8)YesYesYes

Note: See the Alp SDK™ repository, the documentation, the VS Code extension, and the E1M-AEN Hardware Design Guide for bring-up instructions, BSP layout, and SDK API reference. Community support is available at community.alplab.ai.

Reference Schematic​

The minimum carrier-board design below brings up an E1M-AEN with a single 5 V input, reset push-button, status LED, and JTAG/SWD debug header. All other interfaces (Ethernet, USB, MIPI, camera, display) are optional and described in Interfaces.

E1M-AEN Minimum Reference Schematic (figure pending)

Required external components:

  • 5 V power source (≥ TBD A peak) to VDDIN (R1, S1, R2, S2).
  • Bulk decoupling: 1 × 10 μF + 1 × 100 nF close to VDDIN.
  • Reset push-button between PORn (W1) and GND (optional; reference design uses an ALPS SKSGACE010 tactile switch).
  • 10-pin Cortex debug header on JTAG/SWD pads (optional, for development; reference design uses a Samtec FTSH-105-01-F-DV 1.27 mm header).

Optional carrier-board components are described per interface in Interfaces, and in detail in the E1M-AEN Hardware Design Guide.

Compliance & Certifications​

Environmental Compliance​

Table: Environmental Compliance

StandardDescriptionStatus
RoHS 3 (EU 2015/863)Restriction of hazardous substancesCompliant
REACH (EC 1907/2006)Substances of very high concernCompliant
Halogen-free (IEC 61249-2-21)Br + Cl content limitsTBD
Conflict minerals (Dodd-Frank §1502)Tin, tungsten, tantalum, gold sourcingTBD

Wireless Certifications​

See Regulatory Information for the per-region wireless certification IDs.

Functional Safety & Industry-specific Compliance​

The E1M-AEN is not currently certified for safety-critical applications (IEC 61508, ISO 26262, IEC 62304, etc.). Contact Alp Lab for the most recent qualification status.

Mechanical & Footprint Dimensions​

All dimensions are in mm unless otherwise noted.

Table: E1M-AEN Mechanical Dimensions

ParameterSymbolMinMaxUnit
Module lengthL34.935.1mm
Module widthW34.935.1mm
Module height (PCB + tallest component)H—TBDmm
Module massm—TBDg

Recommended PCB Land Pattern​

The recommended carrier-board land pattern follows IPC-7351 nominal density for LGA packages. The module uses a 1.0 mm pad grid with 0.4 mm round, non-solder-mask-defined pads. Pad geometry, stencil aperture, and solder-mask opening details are below.

E1M-AEN Recommended Land Pattern

Table: Land Pattern Parameters

ParameterSymbolValueUnit
Pad pitch (signal grid)p1.0mm
Copper pad diameter—0.40 (dia.)mm
Pad type—Round, NSMD—
Solder-mask opening diameter—0.50 (dia.)mm
Stencil aperture (1:1)—0.40 (dia.)mm
Stencil material—Nano-coated steel mesh—
Stencil thickness (recommended)t0.08mm

Keep-Out Zones​

Two keep-out regions apply, both shown in Land Pattern:

  • Internal keep-out — do not place components on the carrier board directly beneath the module, inside the LGA pad ring. Signal routing beneath the module is permitted, on the top layer between pads and on inner layers. Where additional clearance is required, an internal cutout in the carrier PCB under the module is permitted.
  • External keep-out (courtyard) — keep a 1.0 mm component-free clearance around the module perimeter (37.0 × 37.0 mm overall) for placement tolerance, inspection, and rework access.

RF traces (especially the antenna feed) must be routed away from high-current digital paths.

Module Marking​

Each module is laser-marked on the top side with the following fields:

  • Manufacturer logo (Alp Lab)
  • Product name: E1M-AEN
  • Production date code (YYWW)
  • Serial number

The full MPN is not marked on the module. Wireless regulatory marks (FCC ID, ISED IC, MIC, etc.) are carried on the on-board wireless module, not on the E1M-AEN SoM.

Packaging​

Trays​

The E1M-AEN is supplied exclusively in JEDEC-compliant matrix trays. Tape & reel is not offered for this module.

Tray Drawing (figure pending)

Table: Tray Specifications

ParameterSymbolValueUnit
Tray standard—JEDEC matrix tray—
Units per tray—TBDpcs
Trays per dry-pack bag—TBDpcs

MSL & Handling​

The E1M-AEN is classified to Moisture Sensitivity Level (MSL) TBD per IPC/JEDEC J-STD-020. Modules are shipped in dry-pack with desiccant and a humidity-indicator card.

After opening the dry-pack:

  • Floor life: TBD hours at ≤ 30 °C / ≤ 60% RH.
  • If floor life is exceeded before reflow, bake at TBD °C for TBD h before assembly.

Refer to IPC/JEDEC J-STD-033 for full moisture/reflow handling procedures.

Ordering Information​

MPN Decoder​

Table: E1M-AEN MPN Convention

FieldExampleDescription
FamilyE1MEdge-1 AI Module standard footprint.
Product lineAENAlif Ensemble. Other product lines are denoted by different three-letter codes (e.g. V2N for STM32MP25).
SoC variant7Last digit of the Ensemble variant (Ex).
Memory option0Reserved for memory-config index; 0 = on-die memory only.
Assembly variant1Customer configuration code: selects which optional components are populated (e.g. wireless module, Ethernet PHY, CAN PHY, camera LDOs, connectors). 1 is the standard build; contact Alp Lab for custom assembly variants.

Note: Example: E1M-AEN701 = E1M form factor, Alif Ensemble line, E7 SoC, on-die memory only, standard assembly variant 1.

Ordering Matrix​

Table: Ordering Information

MPNMain CPURAM int.AP cores (A32)NPU (Ethos U55 / U85)ISP / JPEG
E1M-AEN701AE722F80F55D5LS13.5 MB2 × 800 MHz1 × 46 GOPS + 1 × 204 GOPSNo
E1M-AEN501AE512F80F55D5LS13.5 MB1 × 800 MHz1 × 46 GOPS + 1 × 204 GOPSNo
E1M-AEN301AE302F80F55D5LE13.5 MB—1 × 46 GOPS + 1 × 204 GOPSNo
E1M-AEN801AE822FA0E5597LS09.75 MB2 × 800 MHz1 × 46 GOPS + 2 × 204 GOPSYes
E1M-AEN601AE612FA0E5597LS09.75 MB1 × 800 MHz1 × 46 GOPS + 2 × 204 GOPSYes
E1M-AEN401AE402FA0E5597LE09.75 MB—1 × 46 GOPS + 2 × 204 GOPSYes

All configurations above include:

  • 5.5 MB internal MRAM; no external OSPI memory
  • Real-time cores: 1 × 160 MHz + 1 × 400 MHz Cortex-M55
  • Operating temperature: − 40 °C to +85 °C
  • Dual-band (2.4 GHz / 5 GHz) Wi-Fi 6 + BLE 5.4 combo module (BDE-BW3551N)
  • 100 Mbit Ethernet PHY
  • Display backlight driver
  • 2 LDOs for external cameras

RoHS-compliant. Contact Alp Lab for custom assembly variants (lead finish, ball material, etc.).

References & Related Documents​

Table: Related Documents

Ref.TitleSource
[1]Alif Semiconductor Ensemble Series DatasheetAlif Semiconductor
[2]Alif Semiconductor Ensemble Series Reference ManualAlif Semiconductor
[3]E1MTM Specificationgithub.com/alplabai/e1m-spec
[4]E1M-AEN Hardware Design GuideAlp Lab (HG-AEN-001)
[5]Alp SDKTM Repositorygithub.com/alplabai/alp-sdk
[6]Alp SDKTM Documentationdocs.alplab.ai
[7]Alp SDKTM VS Code Extensiongithub.com/alplabai/alp-sdk-vscode
[8]Alp Lab Community Forumcommunity.alplab.ai
[9]BDE-BW3551 Wi-Fi 6 / BLE Module DatasheetBDE Technology
[10]IPC/JEDEC J-STD-020 — Reflow ProfileJEDEC
[11]IPC/JEDEC J-STD-033 — Moisture/Reflow HandlingJEDEC

Revision History​

Table: Revision History

RevisionChangesDate
0.1Initial draft.December 2025
0.2Memory options updated with the correct diagram. Wi-Fi throughput updated to 20 Mbps.April 2026
0.3SoM-typical sections added: Recommended Operating Conditions, ESD & Latch-up, Thermal Characteristics, Power Sequence, Boot Modes, Reset & Module Enable, JTAG/SWD Debug, Wireless RF & Regulatory, Environmental & Reliability, Software Support, Reference Schematic, Compliance, Land Pattern, Packaging (Trays), MPN Decoder, References, Legal Notices.May 2026
0.4Pin tables regenerated and verified against the E1M specification and the production board netlist (all 312 pads). Corrected power pins (VIO_OUT, MODULE_EN/STBY); removed non-existent IO_EN and +3V3_OUT; unused standard pins named leave floating. Wireless module identified as dual-band BDE-BW3551N (CC3551E) with measured RF characteristics. USB 2.0 corrected to the USB2 pins. +V_CAM rails documented as adjustable TLV77201 LDOs. Ordering Matrix simplified; MPN decoder last field corrected to Assembly variant. Updated repository / documentation / contact links. On-module interface ESD/EMI protection removed except on the SDIO / SD-card interface; carrier board must now provide ESD/EMI protection on Ethernet, MIPI DSI, and MIPI CSI. Reflow profile populated (Pb-free, ALPHA OM338, peak 241–244 °C); SMT stencil specified (nano-coated steel mesh, 0.08 mm). Pin-out drawing redrawn as a top-view, colour-coded 312-pad diagram.June 2026
0.5Pin tables re-verified against the production board netlist (E1M-AEN 2626-R2, all 312 pads). IO21 (L3) and IO22 (M3) moved from the Digital Pins table to Not-connected Pins — both pads are unbonded on E1M-AEN, like IO23– IO25. Module Output Rails: corrected VIO_OUT pins from AC1/AC2 (GND) to P1/P2.June 2026
0.6Corrected NPU configuration in the key-features list: E4/E6/E8 carry 2 × Ethos-U55 + 1 × Ethos-U85 (previously mislisted as 3 × Ethos-U55). Verified against the Alif E4/E6/E8 datasheets (454 GOPS total: 46 + 204 + 204). Ordering-table NPU column relabelled Ethos U55 / U85 to reflect the Ethos-U85 (NPU-HG) on the E4/E6/E8 parts.July 2026
0.7Cover page: replaced the block-diagram placeholder with front/back product photos of the E1M-AEN module (rev 1726-R4A).July 2026
0.8Cover page: added open-source Edge-1 AI Module sub-heading; resized cover photos so the Applications section fits on page 1. Absolute Maximum Ratings: added CAN bus (± 58 V), Ethernet MDI (− 0.3 to +4 V), and backlight boost switch node (− 0.3 to +40 V) rows. Removed the duplicated module-supply-voltage row from Electrical Characteristics (retained in Recommended Operating Conditions). Documented interface ESD protection: Ethernet DP83825I (± 5 kV IEC 61000-4-2), CAN TCAN1044AVDRBRQ1 (ISO 10605 ± 8 kV contact / ± 15 kV air), SD-card NVT4858HKZ (IEC 61000-4-2 level 4, ± 8 kV / ± 15 kV). Named the backlight controller (KTD2801ECD-TR, 36 V OVP).July 2026

Disclaimer​

The information in this document is provided in connection with Alp Lab AB products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document. Alp Lab reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time without notice.

Alp Lab products are not authorised for use as critical components in life-support devices, safety-critical equipment, military applications, or any other application where failure of the product could reasonably be expected to result in personal injury or significant property damage, without the express written approval of an officer of Alp Lab AB.

Trademarks​

Alp Lab, Alp SDK™, E1M™, and the Alp Lab logo are trademarks of Alp Lab AB. Arm, Cortex, and Ethos are trademarks of Arm Limited. Alif Semiconductor and Ensemble are trademarks of Alif Semiconductor. All other trademarks are the property of their respective owners.

Export Control​

This product may be subject to export-control regulations. The customer is responsible for complying with all applicable export-control laws.

Contact​

For sales, technical support, or custom-variant requests:

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