E1M-N93
The E1M-N93 is an edge AI module built around the NXP i.MX 9352 SoC. It ships in the 35 × 35 mm E1M form factor and pairs dual Cortex-A55 application cores with an Arm Ethos-U65 neural co-processor.
Module variants
| SKU | Silicon | Status |
|---|---|---|
E1M-NX9101 | NXP i.MX 9352 | preliminary |
i.MX 9352 is the top-of-line i.MX 93 SKU: dual Cortex-A55 @ 1.7 GHz + Cortex-M33 @ 250 MHz + Ethos-U65.
At a glance
| Parameter | Value |
|---|---|
| Application core | Dual Arm Cortex-A55 @ 1.7 GHz |
| Real-time core | Arm Cortex-M33 @ 250 MHz |
| AI accelerator | Arm Ethos-U65 |
| AI throughput | ~0.5 TOPS |
| Power profile | Mid-range, ARMv8-A |
| Form factor | E1M (35 × 35 mm), LGA |
| OS targets | Yocto Linux (A55) · Zephyr / bare-metal (M33) |
What's on the module
| Role | Part | Driver |
|---|---|---|
| Application SoC | NXP i.MX 9352 | (vendor HAL via MCUXpresso / Yocto) |
| PMIC | NXP PCA9451A | <alp/chips/pca9451a.h> (partial) |
| Wi-Fi 6 + BLE | Murata Type 2DL/2EL/2KL/2LL (TBD) | (vendor HAL) |
| Wi-Fi 6 (alt) | NXP IW610 | (vendor HAL) |
Exact populated variant pending; see metadata/e1m_modules/E1M-NX9101.yaml.
PCA9451A PMIC driver
The SDK now carries a first-party PCA9451A driver: chip probe (ACK + DEV_ID read), raw register read/write, INT1 latched-interrupt decode, and per-rail enable/disable plus voltage set/get across all 6 bucks and 5 LDOs. Its register map is taken from the NXP-authored upstream Linux regulator driver, which lists the PCA9451A as sharing the PCA9450-family map.
:::caution Host-tested only — silicon validation deferred The driver has never been exercised on E1M-NX9101 silicon, because the module is not on a bench yet. It is validated only by the host-side unit suite (NULL-argument, uninitialised-context, and table-bounds properties) against a simulated transceiver. Treat every voltage number and sequencing decision as paper-correct, and run your own HiL bring-up before relying on it. :::
Inference
The Ethos-U65 NPU is exposed through the SDK's <alp/inference.h> dispatcher with the CONFIG_ALP_SDK_INFERENCE_BACKEND_ETHOS_U_N93 Kconfig. Models are Vela-compiled TFLite Micro programs.
Boot + identification
E1M-N93 follows the standard two-stage SoM-ID flow: EEPROM manifest + BOARD_ID ADC. See <alp/hw_info.h>.
Status
E1M-N93 is pre-silicon. No E1M-NX9101 module has been on a bench, so nothing on this page is silicon-validated — the chip drivers are host-tested and the register addresses, timing values, and init sequences have not been confirmed against real hardware. Do not ship production firmware against this family without your own HiL campaign.
The cross-family examples (GPIO, I2C, PWM, ADC, UART, RTC, …) target it through the same <alp/...> API as the AEN family; pin maps land alongside the upstream Renesas / NXP HW config writeups.
Getting started
- Mount the E1M-N93 on a compatible E1M board.
- Flash the i.MX 93 Yocto image.
- For M33 development, drop a
board.yamlwithsom.sku: E1M-NX9101.
The SoM preset declares its M33 board target as alp_e1m_nx9101_m33 (no _sm suffix — the i.MX 93 has a single Cortex-M33).
:::caution No Zephyr board implementation yet
alp_e1m_nx9101_m33 is currently declared in metadata only. There is no board definition for it in the SDK's Zephyr board tree, so it is not buildable — not even compile-verified. The target name is referenced by an example and a HiL runner stub in anticipation of the board landing.
:::