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E1M-X V2N-M1 Datasheet

E1M-X V2N-M1 module — frontE1M-X V2N-M1 module — back
E1M-X V2N-M1 module — front (left) and back (right)

The E1M-X V2N-M1 module uses the open-source Edge-1 AI Module (E1MTM) form factor, with a unified pin layout and hardware functionality. This footprint allows users to interchange MPU modules seamlessly while keeping hardware compatible. E1MTM is designed for flexibility, functionality, and longevity in high- and medium-range MCU/MPUs.

Features​

  • Renesas RZ/V2N
    • Quad Arm® Cortex®-A55 (1.8 GHz)
    • Arm Cortex-M33 (200 MHz)
    • Arm MaliTM-C55 ISP (Image Signal Processor)
    • Arm MaliTM-G31 GPU
    • AI Accelerator DRP-AI3 — 4 dense TOPS
    • H.264 / H.265 codec
  • DeepX DX-M1 standalone AI accelerator
    • Up to 25 TOPS AI performance
    • PCIe-attached on-module to the RZ/V2N
    • 2 × LPDDR5X companion memory
    • SPI NAND companion storage
  • Dedicated I/O MCU
    • Arm® Cortex®-M33 (216 MHz)
  • Various memory options
    • LPDDR4X 32-bit 3.2 GT/s, up to 8 GB
    • eMMC — 4 GB to 256 GB
    • SPI NOR – 128 Mbit, boot-supported
  • MIPI Display output — 4 lanes
    • 1920 × 1200 RGB888 @ 60 fps
    • 1280 × 1024 RGB888 @ 120 fps
  • H.264 / H.265 codec
    • H.264 1920 × 1080 × 60 fps
    • H.265 3840 × 2160p × 30 fps
  • 2 × CSI-2 camera inputs — 4 lanes, up to 4K @ 30 fps, 4 virtual channels
  • 2.4 GHz / 5 GHz / 6 GHz Wi-Fi® + Bluetooth® module
    • 802.11 a/b/g/n/ac/ax, 143 Mbps
    • Bluetooth® 5.4 BR/EDR/LE, 3 Mbps
  • 2 × 1 Gbps Ethernet PHY
  • 2 × CAN-BUS PHY
  • PCIe Express® 3.0 — 2 lanes (multiplexed between on-module DeepX M1 and external)
  • Assembly variants available for cost reduction
  • Smallest size in the industry: 45 × 65 mm

Applications​

IoT, industrial, robotics, motor drive, drones, mobile PoS, smart speakers, object detection, medical devices, vending machines, smart home, process control, smart appliances, scanners.

General Description​

Highlights​

The Alp Lab E1M-X V2N-M1 SoM (System-on-Module) is a high-performance, cost-effective solution designed for a range of AI-driven vision applications. Powered by the Renesas RZ/V2N processor and the DeepX standalone AI accelerator, it features an Arm® Quad Cortex®-A55 (1.8 GHz) CPU, an integrated AI accelerator, and a 4K encoder/decoder, making it optimised for vision-based tasks. The E1M-X V2N-M1 SoM supports up to two cameras via 2 × 4-lane MIPI CSI-2 connections and offers customisable options such as on-board Wi-Fi / Bluetooth, multiple memory and storage capacities, and PHY configurations.

Block Diagram​

E1M-X V2N-M1 Block Diagram (figure pending)

Module Variants​

The E1M-X V2N-M1 family ships in two MPN variants. Both populate the full V2N silicon stack plus the on-module DeepX DX-M1 accelerator and its companion memory; they differ only in the main-memory tier. See Ordering Information for the full ordering matrix and MPN decoder.

Table: E1M-X V2N-M1 Variant Summary

MPNRenesas partLPDDR4XeMMCAI capability
E1M-V2M101R9A09G056N44GBG#AC032 GbiteMMC 5.1, 32 GbitV2N: 4 TOPS + DX-M1: 25 TOPS
E1M-V2M102R9A09G056N44GBG#AC064 GbiteMMC 5.1, 128 GbitV2N: 4 TOPS + DX-M1: 25 TOPS

Renesas RZ/V2N MPU​

The RZ/V2N is a vision-AI microprocessor (MPU) with Renesas' proprietary AI accelerator (DRP-AI3) supporting up to 15 TOPS of AI performance. Its CPUs are quad Arm® Cortex®-A55 (1.8 GHz) and Arm Cortex-M33 (200 MHz). The RZ/V2N is equipped with an ISP (Image Signal Processor) and dual-channel MIPI® CSI-2® camera interfaces for supporting dual-camera signal processing, which is crucial for realising vision systems. It is also equipped with high-speed interfaces such as PCIe® and USB 3.2, allowing for the expansion of external devices. The RZ/V2N is an ideal microprocessor for applications requiring both low power consumption and advanced AI inference, such as DMS (Driver Monitoring System), monitoring cameras, mobile robots, and more.

This document should be read together with the V2N datasheet from Renesas.

Renesas RZ/V2N MPU Block Diagram (figure pending)

Key MPU features:

  • Cortex-A55 (1.8 GHz) × 4 cores
  • Cortex-M33 (200 MHz) × 1 core
  • AI Accelerator DRP-AI
  • Arm MaliTM-C55 ISP (option)
  • 1.5 MB on-chip SRAM
  • LPDDR4 / LPDDR4X memory interface
  • Gigabit Ethernet 2 ch
  • USB 2.0 interface 1 ch (Host/Function)
  • USB 3.2 (Gen2) interface 1 ch (Host only)
  • PCIe interface (Gen3, 2-lane) 1 ch
  • MIPI CSI-2 camera interface 2 ch
  • CAN interface (CAN FD) 6 ch
  • AD converter 24 ch

DeepX DX-M1 — Standalone AI Accelerator​

The DX-M1 is a 25 TOPS AI processor with class-leading power efficiency. DeepX designed the DX-M1 with the highest IPS (inference-per-second) per watt as a main goal. It is used as an AI accelerator with a host. The DX-M1 NPU is designed for deep-learning algorithm coverage including computer-vision tasks such as image classification, object detection, and identification of audio streams (e.g. keyword spotting). To speed up software development, DeepX provides a comprehensive software environment that includes an SDK and a model-zoo verified on DX-M1. The DX-COMTM tool automatically converts neural networks built in popular frameworks (PyTorch, ONNX, ...) into optimised executable code for the DX-M1.

DeepX DX-M1 Block Diagram (figure pending)

Pin Diagram and List​

The E1M-XTM standard defines the primary pin functions; the pin-out below follows that standard. Pins can be reassigned to alternate functions in software, but hardware compatibility with other E1M-X variants will no longer hold because each MCU/MPU has a different pin structure and peripheral mapping.

E1M-X V2N-M1 Pin-out (top view, 496-pad LGA)

Power & Control Pins​

Table: E1M-X V2N-M1 Power & Control Pins

Pin NumberPin NameDescription
A13, K63, AQ15, M1, M63, O63, A18, AQ18, P1, A20, AQ20, S1, A22, U63, A26, AA63, AQ29, AC1, AQ6, D1, A35, AG1, AG63, AQ35, A37, AI1, AM1, AM63, AO1, AQ1, A46, AQ46, AR63, A48, AQ48, A8, A54, AQ54, AQ55, A56, AQ61, A62, AQ9, G1, G63, I63, AQ12, J1, A1, A3, A63, AQ3, C3, K64, M64, O64, U64, AA64, AG64, AM64, AR64, G64, I64, A64, AR16, AR18, AR20, AR30, AR6, AR35, AR46, AR48, AR54, AR55, AR61, AR12, AR3, B13, K2, B18, P2, B20, S2, B23, B26, Z2, AC2, B35, AI2, B37, AM2, AN2, AO2, E2, AP2, AQ2, AR2, B46, B48, B8, B54, B56, B62, H2, B3GNDConnect to ground.
W1, W2VIO_OUT+1V8 output for I/O power. Up to TBD mA.
T1, U1, V1, T2, U2, V2VDD_5V_IN+5 V main supply input to the module.
AQ25+S_CAPExternal super-capacitor connection.
Y2BOOT0Boot selection for Renesas RZ/V2N. See .
X2BOOT1
X1BOOT2Not connected. Leave floating.
Y1BOOT3Boot CPU selection. High: RZ/V2N internal CA55 boot. Low: RZ/V2N internal CM33 boot.
AL1JTAG_nRSTJTAG / SWD pins for programming and debug.
AJ1JTAG_TCK / SWDCLK
AJ2JTAG_TDI
AK2JTAG_TDO
AK1JTAG_TMS / SWDIO
AA1MODULE_ENModule enable. Open-drain. Pulled up internally to VDD. Connect to GND to disable the module; leave floating if not used.
Z1PORnReset input. Open-drain. Pulled up internally to 1V8. Pull low to reset the module; leave floating if not used.
AB1MODULE_STBYModule stand-by request. Open-drain, pulled up internally to 1V8. Leave floating if not used.
A2USB_CC1USB Type-C Configuration Channel 1.
B2USB_CC2USB Type-C Configuration Channel 2.
AQ30SD_VDD_OUTSD-card voltage output. Connect to SD card VDD.
H64+V_CAM0CAM0 LDO output. 0.6 V to 3.3 V, 300 mA max.
J64+V_CAM1CAM1 LDO output. 0.6 V to 3.3 V, 300 mA max.
L64+V_CAM2CAM2 LDO output. 0.6 V to 3.3 V, 300 mA max.
N64+V_CAM3CAM3 LDO output. 0.6 V to 3.3 V, 300 mA max.
H63CAM_VFB0Feedback node for +V_CAM0. Place divider close to the module pin.
J63CAM_VFB1Feedback node for +V_CAM1. Place divider close to the module pin.
L63CAM_VFB2Feedback node for +V_CAM2. Place divider close to the module pin.
N63CAM_VFB3Feedback node for +V_CAM3. Place divider close to the module pin.
B55BL_LED_A / BL_PWMBL_LED_A: anode of backlight. BL_PWM: connect to backlight driver.
A55BL_LED_KCathode of backlight. Leave floating if BL_PWM is used.

Analog Pins​

Table: E1M-X V2N-M1 Analog Pins

Pin NumberPin NamePeripheralDescription
A17ANA_S0AINAnalog input channels, referenced to 1V8.
B17ANA_S1
A16ANA_S2
B16ANA_S3
A15ANA_S4
B15ANA_S5
A14ANA_S6
B14ANA_S7
A19DAC0DAC0Analog output channels, referenced to 1V8.
B19DAC1DAC1
AR1ANT_2.4GHz / NCANT: module antenna output for Wi-Fi 6 and BLE. Route 50 Ω trace. NC: leave floating.

Digital Pins​

Table: E1M-X V2N-M1 Digital Pins

Pin NumberPin NamePeripheralDescription
AR21IO8GPIO / SMCUGeneral purpose I/O, controlled by the secondary MCU on E1M-X.
AQ21IO9
AR22IO10
AQ22IO11
AR23IO12
AQ23IO13
AR24IO14
AQ24IO15
AR25IO16
F63IO25
F64IO26
AN63IO27
AN64IO28
AO63IO29
AO64IO30
AP63IO31
AP64IO32
AQ64IO34
A25IO35
AQ16RTC_CLKOUTRTCReal-time clock output.
AC62DBG_TXDBGOn-module debug UART transmit.
AD62DBG_RXOn-module debug UART receive.
L2IO0GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
M2IO1GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
N2IO2GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
O2IO3GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
AF2IO4GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
AG2IO5GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
AL2IO6GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
AQ26IO17GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
AR26IO18GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
AQ27IO19GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
AR27IO20GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
AQ28IO21GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
AR28IO22GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
AR29IO24GPIOGeneral-purpose IO. Routed to the on-module DX-M1; available as carrier GPIO after a DeepX software patch.
AR9AUDIO_CLK—Audio clock output.
AQ7PDM_C0PDM0Digital microphone interface. PDM_C is the clock, PDM_D is the data line.
AR7PDM_D0
AQ8PDM_C1PDM1Digital microphone interface.
AR8PDM_D1
AQ5I2S0_SCLKI2S0I2S interface.
AQ4I2S0_SDI
AR4I2S0_SDO
AR5I2S0_WS
AR11I2S1_SCLKI2S1I2S interface.
AR10I2S1_SDI
AQ10I2S1_SDO
AQ11I2S1_WS
AH1I2C0_SCLI2C0I2C interface.
AH2I2C0_SDA
AQ47I2C1_SCLI2C1I2C interface.
AR47I2C1_SDA
E64I2C2_SCLI2C2I2C interface.
E63I2C2_SDA
A24I2C3_SCLI2C3I2C interface, controlled by the secondary MCU on E1M-X.
A23I2C3_SDA
AQ19I3C_SCLI3CI3C interface.
AR19I3C_SDA
AE1SPI0_CS0SPI0SPI interface.
AF1SPI0_CS1
AD1SPI0_MISO
AD2SPI0_MOSI
AE2SPI0_SCLK
AR14SPI1_CS0SPI1SPI interface.
AR13SPI1_CS1
AQ13SPI1_MISO
AQ14SPI1_MOSI
AR15SPI1_SCLK
C64SPI2_CS0SPI2SPI interface.
D64SPI2_CS1
B63SPI2_MISO
B64SPI2_MOSI
C63SPI2_SCLK
AB2UART0_RXUART0UART interface.
AA2UART0_TX
AR17UART1_RXUART1UART interface.
AQ17UART1_TX
B21CAN0H / CAN0_TXCAN0CAN-BUS interface.
B22CAN0L / CAN0_RX
B24CAN1H / CAN1_TXCAN1CAN-BUS interface.
B25CAN1L / CAN1_RX
A21CAN_STBYCANStandby control for CAN-BUS.
A7PWM0PWMPWM output, controlled by the secondary MCU on E1M-X.
B7PWM1
A6PWM2
B6PWM3
A5PWM4
B5PWM5
A4PWM6
B4PWM7
A12ENC0_XENC0Encoder input.
B12ENC0_Y
A11ENC1_XENC1Encoder input.
B11ENC1_Y
A10ENC2_XENC2Encoder input.
B10ENC2_Y
A9ENC3_XENC3Encoder input.
B9ENC3_Y
AR56ETH0_DD_NETH0Ethernet interface. 1 Gbit PHY connection.
AQ56ETH0_DD_P
AR57ETH0_DC_N
AQ57ETH0_DC_P
AR58ETH0_DB_N
AQ58ETH0_DB_P
AR59ETH0_DA_N
AQ59ETH0_DA_P
AQ60ETH0_LED0
AR60ETH0_LED1
AR49ETH1_DD_NETH1Ethernet interface. 1 Gbit PHY connection.
AQ49ETH1_DD_P
AR50ETH1_DC_N
AQ50ETH1_DC_P
AR51ETH1_DB_N
AQ51ETH1_DB_P
AR52ETH1_DA_N
AQ52ETH1_DA_P
AQ53ETH1_LED0
AR53ETH1_LED1
AQ31SD_CLKSD0SD card or eMMC interface.
AR31SD_CMD
AQ32SD_D0
AR33SD_D1
AQ33SD_D2
AR34SD_D3
AQ34SD_DET
AR32SD_RST
T64CSI0_0_NCSI0MIPI CSI camera interface.
T63CSI0_0_P
S64CSI0_1_N
S63CSI0_1_P
Q64CSI0_2_N
Q63CSI0_2_P
P64CSI0_3_N
P63CSI0_3_P
R64CSI0_C_N
R63CSI0_C_P
Z64CSI1_0_NCSI1MIPI CSI camera interface.
Z63CSI1_0_P
Y64CSI1_1_N
Y63CSI1_1_P
W64CSI1_2_N
W63CSI1_2_P
V64CSI1_3_N
V63CSI1_3_P
X64CSI1_C_N
X63CSI1_C_P
B61DSI0_0_NDSI0MIPI DSI display interface.
A61DSI0_0_P
B60DSI0_1_N
A60DSI0_1_P
B59DSI0_2_N
A59DSI0_2_P
B58DSI0_3_N
A58DSI0_3_P
B57DSI0_C_N
A57DSI0_C_P
B47PCIE0_CLK_NPCIE0PCIe interface (multiplexed with on-module DeepX M1).
A47PCIE0_CLK_P
B42PCIE0_RX0_N
A42PCIE0_RX0_P
B43PCIE0_RX1_N
A43PCIE0_RX1_P
B38PCIE0_TX0_N
A38PCIE0_TX0_P
B39PCIE0_TX1_N
A39PCIE0_TX1_P
C1USB0_30_D_NUSB0USB 3.0 interface.
B1USB0_30_D_P
F1USB0_30_RX0_N
E1USB0_30_RX0_P
I1USB0_30_TX0_N
H1USB0_30_TX0_P
G2USB2_20_IDUSB2USB 2.0 interface.
J2USB2_20_N
I2USB2_20_P
F2USB2_20_VBUS

Not Connected Pins​

These pins carry an E1M-XTM standard function that is not implemented on the V2N-M1 module. They retain their standard name for cross-variant compatibility and must be left floating.

Table: E1M-X V2N-M1 Not-connected Pins

Pin NumberPin NameDescription
A27PCIE1_TX0_PLeave floating.
A28PCIE1_TX1_PLeave floating.
A29PCIE1_TX2_PLeave floating.
A30PCIE1_TX3_PLeave floating.
A31PCIE1_RX0_PLeave floating.
A32PCIE1_RX1_PLeave floating.
A33PCIE1_RX2_PLeave floating.
A34PCIE1_RX3_PLeave floating.
A36PCIE1_CLK_PLeave floating.
A40PCIE0_TX2_PLeave floating.
A41PCIE0_TX3_PLeave floating.
A44PCIE0_RX2_PLeave floating.
A45PCIE0_RX3_PLeave floating.
A49DSI1_C_PLeave floating.
A50DSI1_3_PLeave floating.
A51DSI1_2_PLeave floating.
A52DSI1_1_PLeave floating.
A53DSI1_0_PLeave floating.
AA3LCD_B23Leave floating.
AB3LCD_HSYNCLeave floating.
AB63CSI2_3_PLeave floating.
AB64CSI2_3_NLeave floating.
AC3LCD_VSYNCLeave floating.
AC63CSI2_2_PLeave floating.
AC64CSI2_2_NLeave floating.
AD3NCLeave floating.
AD63CSI2_C_PLeave floating.
AD64CSI2_C_NLeave floating.
AE3NCLeave floating.
AE63CSI2_1_PLeave floating.
AE64CSI2_1_NLeave floating.
AF3NCLeave floating.
AF63CSI2_0_PLeave floating.
AF64CSI2_0_NLeave floating.
AG3NCLeave floating.
AH3NCLeave floating.
AH63CSI3_3_PLeave floating.
AH64CSI3_3_NLeave floating.
AI3NCLeave floating.
AI63CSI3_2_PLeave floating.
AI64CSI3_2_NLeave floating.
AJ3NCLeave floating.
AJ63CSI3_C_PLeave floating.
AJ64CSI3_C_NLeave floating.
AK3NCLeave floating.
AK63CSI3_1_PLeave floating.
AK64CSI3_1_NLeave floating.
AL3NCLeave floating.
AL63CSI3_0_PLeave floating.
AL64CSI3_0_NLeave floating.
AM3NCLeave floating.
AN1ANT_6GHzLeave floating.
AN3NCLeave floating.
AO3NCLeave floating.
AP1ANT_5GHzLeave floating.
AP3NCLeave floating.
AQ36NCLeave floating.
AQ37NCLeave floating.
AQ38NCLeave floating.
AQ39NCLeave floating.
AQ40NCLeave floating.
AQ41NCLeave floating.
AQ42NCLeave floating.
AQ43NCLeave floating.
AQ44NCLeave floating.
AQ45NCLeave floating.
AQ63IO33Leave floating.
AR36NCLeave floating.
AR37NCLeave floating.
AR38NCLeave floating.
AR39NCLeave floating.
AR40NCLeave floating.
AR41NCLeave floating.
AR42NCLeave floating.
AR43NCLeave floating.
AR44NCLeave floating.
AR45NCLeave floating.
B27PCIE1_TX0_NLeave floating.
B28PCIE1_TX1_NLeave floating.
B29PCIE1_TX2_NLeave floating.
B30PCIE1_TX3_NLeave floating.
B31PCIE1_RX0_NLeave floating.
B32PCIE1_RX1_NLeave floating.
B33PCIE1_RX2_NLeave floating.
B34PCIE1_RX3_NLeave floating.
B36PCIE1_CLK_NLeave floating.
B40PCIE0_TX2_NLeave floating.
B41PCIE0_TX3_NLeave floating.
B44PCIE0_RX2_NLeave floating.
B45PCIE0_RX3_NLeave floating.
B49DSI1_C_NLeave floating.
B50DSI1_3_NLeave floating.
B51DSI1_2_NLeave floating.
B52DSI1_1_NLeave floating.
B53DSI1_0_NLeave floating.
C2USB0_30_VBUSLeave floating.
C62CAM_HSYNCLeave floating.
D2USB0_30_IDLeave floating.
D3LCD_B0Leave floating.
D62CAM_VSYNCLeave floating.
D63NCLeave floating.
E3LCD_B1Leave floating.
E62CAM_PCLKLeave floating.
F3LCD_B2Leave floating.
F62CAM_XVCLKLeave floating.
G3LCD_B3Leave floating.
G62CAM_D1Leave floating.
H3LCD_B4Leave floating.
H62CAM_D2Leave floating.
I3LCD_B5Leave floating.
I62CAM_D3Leave floating.
J3LCD_B6Leave floating.
J62CAM_D4Leave floating.
K1USB1_30_D_PLeave floating.
K3LCD_B7Leave floating.
K62CAM_D5Leave floating.
L1USB1_30_D_NLeave floating.
L3LCD_B8Leave floating.
L62CAM_D6Leave floating.
M3LCD_B9Leave floating.
M62CAM_D7Leave floating.
N1USB1_30_RX0_PLeave floating.
N3LCD_B10Leave floating.
N62CAM_D8Leave floating.
O1USB1_30_RX0_NLeave floating.
O3LCD_B11Leave floating.
O62CAM_D9Leave floating.
P3LCD_B12Leave floating.
P62CAM_D10Leave floating.
Q1USB1_30_TX0_PLeave floating.
Q2USB1_30_VBUSLeave floating.
Q3LCD_B13Leave floating.
Q62CAM_D11Leave floating.
R1USB1_30_TX0_NLeave floating.
R2USB1_30_IDLeave floating.
R3LCD_B14Leave floating.
R62CAM_D12Leave floating.
S3LCD_B15Leave floating.
S62CAM_D13Leave floating.
T3LCD_B16Leave floating.
T62CAM_D14Leave floating.
U3LCD_B17Leave floating.
U62CAM_D15Leave floating.
V3LCD_B18Leave floating.
V62CAM_D16Leave floating.
W3LCD_B19Leave floating.
X3LCD_B20Leave floating.
Y3LCD_B21Leave floating.
Z3LCD_B22Leave floating.

Reserved Pins​

Table: E1M-X V2N-M1 Reserved Pins

Pin NumberPin NameDescription
W62, X62, Y62, Z62, AA62, AB62, AE62, AF62, AG62, AH62, AI62, AJ62, AK62, AL62, AM62, AN62, AO62, AP62, AQ62, AR62RSVDDo not connect. Used for production purposes.

Specifications​

Absolute Maximum Ratings​

Warning: Stresses beyond Absolute Maximum Ratings may cause permanent damage. Operation at these conditions is not implied.

Table: E1M-X V2N-M1 Absolute Maximum Ratings

ParameterSymbolMinMaxUnit
Power-supply voltageVDDIN to GND− 0.36.0V
Analog input voltageV(ANA_Sx)− 0.31.98V
Digital IO (1V8)− 0.31.98V

The module is specified to meet the Electrical Characteristics in Electrical Characteristics over the conditions below. Operation outside this range is not guaranteed.

Table: E1M-X V2N-M1 Recommended Operating Conditions

ParameterSymbolMinTypMaxUnit
Module supply voltageVDDIN4.55.05.5V
Ambient operating temperatureTA− 40—+85°C
Junction operating temperatureTJ——TBD°C
Relative humidity (operating, non-condensing)RHTBD—TBD%

Electrical Characteristics​

Table: E1M-X V2N-M1 Electrical Characteristics

SymbolDescriptionMinNomMaxUnit
Power supply
VDDINModule power supply4.55.05.5V
IDDMAXMaximum IDD currentTBD
SD_VDD_OUTSD-card supply (high-speed mode)1.8V
SD_VDD_OUTSD-card supply (low-speed mode)3.3V
Analog inputs
V(AINx)Input voltage0—1.8V
Digital IOs
VOLLow-level output voltage
VOHHigh-level output voltage
VILLow-level input voltage
VIHHigh-level input voltage
Camera LDOs
+V_CAM0CAM0 LDO output0.6—3.3V
+V_CAM1CAM1 LDO output0.6—3.3V
+V_CAM2CAM2 LDO output0.6—3.3V
+V_CAM3CAM3 LDO output0.6—3.3V

ESD & Latch-up Ratings​

ESD ratings apply at module-level — i.e. directly to the LGA pads as exposed to a carrier-board assembly process. Customer ESD protection requirements on the carrier board are described in the relevant interface sub-sections.

Table: E1M-X V2N-M1 ESD & Latch-up Ratings

ParameterStandardMinMaxUnit
Human Body Model (HBM)ANSI/ESDA/JEDEC JS-001—TBDV
Charged Device Model (CDM)ANSI/ESDA/JEDEC JS-002—TBDV
Latch-upJESD78—TBDmA

Thermal Characteristics​

The E1M-X V2N-M1 dissipates heat through both the Renesas RZ/V2N SoC and the on-module DeepX DX-M1 accelerator. Sustained AI workloads run both heat sources concurrently; an active heatsink or forced-air cooling is recommended above ~50% DX-M1 utilisation at +25 °C ambient. Thermal-resistance figures below assume a 45 × 65 mm module mounted on a 4-layer FR4 carrier with a ground-plane heatsink.

Table: E1M-X V2N-M1 Thermal Characteristics

ParameterSymbolTypMaxUnit
Thermal resistance, junction-to-ambient (RZ/V2N, still air)θJA,V2NTBD—°C/W
Thermal resistance, junction-to-ambient (DX-M1, still air)θJA,M1TBD—°C/W
Maximum junction temperature (RZ/V2N)TJ,max,V2N—TBD°C
Maximum junction temperature (DX-M1)TJ,max,M1—TBD°C
Power dissipation derating (above +85 °C)PDTBD—mW/°C

V2N-M1 power-dissipation derating curve (DRP-AI3 + DX-M1 combined) (figure pending)

Power​

Power Architecture​

All power rails on the module are generated and managed on-board from a single externally-supplied 5 V input on VDD_5V_IN. On-module power management is performed by an I2C-controlled PMIC (Renesas DA9292) plus a GD32 supervisor MCU (Cortex-M33 @ 216 MHz) that orchestrates rail sequencing for the RZ/V2N, the DeepX DX-M1, and the M1's companion LPDDR5X memory.

The E1M-X V2N-M1 includes all necessary decoupling capacitors. Additional decoupling capacitors on the carrier board may improve performance further.

The module exposes two regulated output rails to the carrier:

Table: Module Output Rails

RailPinsVoltageMax currentPurpose
VIO_OUTW1, W21.8 V ± 5%TBD mAI/O reference for carrier-side level shifters.
SD_VDD_OUTAQ301.8 / 3.3 V auto300 mAmicroSD slot supply; auto-switches for high/low-speed modes.

E1M-X V2N-M1 Power Architecture Diagram (figure pending)

Note: The DX-M1's internal power rails (LPDDR5X, NPU core, SPI NAND) are entirely on-module and not exposed to the carrier. The GD32 supervisor brings them up sequentially after VDD_5V_IN stabilises.

Power-Up & Reset Sequence​

The recommended power-up sequence is:

  1. Apply 5 V to VDD_5V_IN.
  2. Release MODULE_EN (let internal pull-up hold high).
  3. Release PORn (let internal pull-up hold high).
  4. Wait for the on-module power-up to complete. Internal rails (including the DX-M1 sub-system) stabilise within ~TBD ms of MODULE_EN release (longer than V2N because of the M1's LPDDR5X bring-up). The module exposes no ready-strobe output, so allow this fixed delay before driving signals into the module.
  5. Begin communication with the module.

V2N-M1 Power-Up Timing Diagram (figure pending)

Note: For power-down, drive MODULE_EN low and remove VDD_5V_IN. The module does not require a controlled power-down sequence at the carrier-board level.

Power Consumption​

Numbers below are typical at TA = +25 °C, VDDIN = 5.0 V. The DX-M1 baseline draw (always on once the module has powered up) is the main delta vs the V2N family.

Table: E1M-X V2N-M1 Power Consumption (typical)

ModeDescriptionMinTypMaxUnit
Active
A55 quad + DRP-AI3 + DX-M1 @ full loadCombined AI inference at 29 TOPS—TBDTBDmA
A55 quad + DX-M1 onlySingle-NPU offload—TBDTBDmA
A55 quad + DRP-AI3 only (DX-M1 idle)V2N-equivalent workload—TBDTBDmA
A55 quad @ 1.8 GHz, no AIGeneral Linux compute—TBDTBDmA
Active, with dual Ethernet + PCIe SSD + display + cameraFull-feature workload—TBDTBDmA
Low-power
Idle (DX-M1 in reset)Cores halted, M1 gated—TBD—mA
SleepRetention only, RTC running—TBD—μA
Shutdown (MODULE_EN low)Module disabled—TBD—μA

Boot Settings​

E1M-X V2N-M1 supports several boot options selected by the BOOT0–BOOT3 strap pins on the carrier.

Table: E1M-X V2N-M1 Boot Options

BOOT1BOOT0Boot modeDeviceCA55 bootCM33 boot
00Mode 0eSD (3.3 V for execution)SupportedNot supported
01Mode 1eMMC (I/O voltage 1.8 V)SupportedNot supported
10Mode 2QSPI NOR (I/O voltage 1.8 V)SupportedSupported
11Mode 3SCIF downloadSupportedSupported

Note: BOOT2 is fixed at 1.

Boot Modes​

The Renesas RZ/V2N samples the four boot-strap pins (BOOT0–BOOT3) at the rising edge of PORn. BOOT0/BOOT1 select the boot source; BOOT2 is fixed at 1 on the V2N family; BOOT3 selects the boot CPU (high = CA55, low = CM33). See Boot Settings for the full mapping.

The carrier-board MUST drive BOOT0/BOOT1 (typically via a 2-position DIP switch with 10 kΩ pull-downs). The other two strap pins may be hard-strapped.

The DeepX DX-M1 has no carrier-visible boot configuration — it boots autonomously under control of the GD32 supervisor whenever the SoM 5 V rail is up and MODULE_EN is high. The M1 is not affected by the BOOT* pins.

Note: For details on the secure-boot signing flow, see AN-010: Secure Boot and Code Signing. For the DX-M1 first-inference walkthrough see AN-009: DeepX DX-M1 First Inference.

E1M-X V2N-M1 Boot Flow (figure pending)

Reset & Module Enable​

The E1M-X V2N-M1 exposes the same control signals as V2N. Asserting PORn resets both the RZ/V2N and the on-module DX-M1; software does not need to manage the M1 reset separately.

Table: Reset & Module Enable Signals

PinDirectionDescription
MODULE_ENInput, open-drainInternally pulled up to VDDIN. Pull low to disable the module (forces shutdown of both V2N and DX-M1). Leave floating if unused.
PORnInput, open-drainInternally pulled up to 1V8. Pull low to issue a power-on reset to both the RZ/V2N and the DX-M1. Minimum low-pulse width: TBD μs.
MODULE_STBYInput, open-drainStandby request. Reference firmware enters RTC-only standby; the DX-M1 enters its lowest-power retention state.

V2N-M1 Reset Timing Diagram (figure pending)

JTAG / SWD Debug​

The E1M-X V2N-M1 exposes a 5-pin JTAG / SWD interface for programming and debug of the RZ/V2N. Signals operate at 1.8 V; carrier-board level shifters are required for 3.3 V debug probes. The DeepX DX-M1's debug interface is not exposed to the carrier — its bring-up is autonomous and software-debuggable from the RZ/V2N host over PCIe.

Table: JTAG / SWD Pinout

PinSignalDescription
AL1JTAG_nRSTActive-low reset to the SoC debug logic.
AJ1JTAG_TCK / SWDCLKTest clock (JTAG) or serial-wire clock (SWD).
AJ2JTAG_TDITest data in (JTAG only).
AK2JTAG_TDOTest data out (JTAG only).
AK1JTAG_TMS / SWDIOTest mode select (JTAG) or serial-wire I/O (SWD).

Note: Alp Lab recommends exposing the JTAG/SWD pins on a 10-pin Cortex-M debug header on the carrier board. Refer to UG-E1M-X-001 §5.1 for the reference connector pinout.

Reference JTAG / SWD Header Pinout (figure pending)

Interfaces​

The E1M-X offers a wide set of interfaces to accommodate diverse system requirements:

  • General-purpose digital I/O (GPIO)
  • I2C, I3C, SPI, and UART serial buses
  • USB 2.0 / 3.2 Gen 2 ports
  • CAN FD (Flexible Data-rate)
  • PCI Express Gen 3
  • MIPI CSI and DSI for camera and display connectivity
  • Dual Gigabit Ethernet with IEEE 1588 support

Ethernet​

E1M-X V2N-M1 has two 1 Gbit Ethernet PHYs: the Realtek RTL8211FDI. The interfaces do not include on-module EMI or ESD protection; the user must provide external magnetics transformers, connectors, and EMI/ESD protection on the carrier board.

E1M-X V2N-M1 Ethernet PHY Connection (figure pending)

USB​

E1M-X V2N-M1 has one USB 2.0 and one USB 3.2 Gen 2 interface. USB 2.0 supports Host/Function; USB 3.2 is Host-only.

Table: E1M-X V2N-M1 USB Interface

Pin NumberPin NamePeripheralDescription
C1USB0_30_D_NUSB0Route USB_N and USB_P as a differential pair with 90 Ω impedance.
B1USB0_30_D_P
F1USB0_30_RX0_N
E1USB0_30_RX0_P
I1USB0_30_TX0_N
H1USB0_30_TX0_P
G2USB2_20_IDUSB2Low: Host mode. NC: Device mode.
J2USB2_20_NRoute USB_N and USB_P as a differential pair with 90 Ω impedance.
I2USB2_20_P
F2USB2_20_VBUSConnect to USB VBUS 5 V.

PCIe​

Renesas RZ/V2N has one PCIe® Gen3 2-lane interface. The PCIe interface is used to communicate with the standalone AI accelerator DeepX-M1 to sustain AI-computation performance. However, to increase user flexibility, the PCIe interface is multiplexed to work either with DeepX-M1 or exit the module for external connections.

E1M-X V2N-M1 PCIe MUX Connection (figure pending)

Serial Interfaces​

I2C​

E1M-X has four I2C interfaces. Refer to the Renesas RZ/V2N series datasheet for full details. External pull-ups are required.

Note: The I2C3 interface is connected to the secondary MCU on E1M-X. It is handled by the Alp SDKTM from the main MPU.

I3C​

E1M-X has one I3C interface. Refer to the Renesas RZ/V2N series datasheet for full details. External pull-ups are required.

UART​

E1M-X has two UART interfaces. Refer to the Renesas RZ/V2N series datasheet for full details.

SPI​

E1M-X has three SPI interfaces. Refer to the Renesas RZ/V2N series datasheet for full details.

I2S​

E1M-X has two I2S interfaces. Refer to the Renesas RZ/V2N series datasheet for full details.

CAN Bus​

E1M-X includes two optional CAN-BUS PHYs to simplify carrier-board hardware design. When the internal PHY is used, the user must add termination, ESD, and EMI protection components on the carrier board.

E1M-X V2N-M1 CAN-BUS Connection (figure pending)

SD Card​

E1M-X supports an external μSD card over the SDIO interface. The SDIO lines have ESD protection and 22 Ω series resistors on the module, plus 1 MΩ pull-ups. SD-card power is supplied by E1M-X via SD_VDD_OUT; the voltage switches automatically between high-speed and low-speed modes.

E1M-X V2N-M1 SD Card Interface (figure pending)

MIPI DSI Display & Backlight Controller​

Renesas RZ/V2N has a 4-lane MIPI DSI interface for an external display, supporting up to FHD resolution. The RZ/V2N also includes an internal 3D GPU (Arm MaliTM-G31) that can accelerate display rendering.

E1M-X V2N-M1 Display Connection with Backlight Driver (figure pending)

E1M-X has a backlight driver for external screens, controlled directly from the Alp SDKTM. The driver is optional; outputs are configured via the BL_LED_A and BL_LED_K pins. The driver supports up to 10 LEDs in series, or 2P6S.

If the backlight driver is not needed, the BL_PWM signal can be exposed directly to drive an external backlight driver. The MIPI DSI interface does not include on-module EMI or ESD protection; protect the DSI lanes with a low-capacitance TVS array on the carrier board.

The feedback resistor value can be computed from the required LED current:

I_LED = 95 mV / R_FB

MIPI CSI Camera​

Renesas RZ/V2N has two 4-lane MIPI CSI interfaces for external cameras. The RZ/V2N also includes an internal ISP (Arm MaliTM-C55) that can accelerate image processing.

E1M-X V2N-M1 Camera Connection with LDO (figure pending)

E1M-X supports direct camera implementation via on-board LDOs. Place the feedback resistors as close as possible to the CAM_VFBx pins. The MIPI CSI interface does not include on-module EMI or ESD protection; protect the CSI lanes with a low-capacitance TVS array on the carrier board.

The output voltage is set by the divider:

V_CAM = 0.6 V × (1 + R1 / R2)

To minimise feedback-pin current error, set the divider current to 100 × the maximum feedback-pin current. The resulting series resistance limit is:

R1 + R2 ≤ V_OUT / (I_FB × 100)

Microphone – PDM​

E1M-X supports up to 4 digital microphones over 2 PDM interfaces.

E1M-X V2N-M1 PDM Connection Diagram (figure pending)

Refer to the E1M-X hardware design guide for full details.

Analog Inputs​

E1M-X has 8 analog input channels (ADC). The analog inputs are connected to the secondary MCU, which has a 12-bit ADC with a 5.3 Msps sampling rate. Analog inputs are referenced to 1V8.

Refer to the secondary-MCU datasheet for electrical characteristics. TBD.

Analog Outputs​

E1M-X has 2 analog output channels (DAC). The analog outputs are connected to the secondary MCU, which has a 12-bit DAC with a 1 kHz sampling rate. Analog outputs are referenced to 1V8.

Refer to the secondary-MCU datasheet for electrical characteristics. TBD.

Components​

Wireless Module & Antenna​

E1M-X V2N-M1 integrates the Murata LBEE5HY2FY Wi-Fi 6 + BLE 5.4 combo module (based on Infineon CYW55513) on-module per E1M Spec §6.5. The antenna pads exit on a 50 Ω controlled-impedance trace; the carrier provides either a U.FL connector or a PCB antenna.

E1M-X V2N-M1 Antenna Connection (figure pending)

RF Characteristics​

Table: E1M-X V2N-M1 Wi-Fi 6 / BLE RF Characteristics

SymbolDescriptionMinTypMaxUnit
Wi-Fi 6 (802.11ax)
fop,2.42.4 GHz band operating range2400—2483.5MHz
fop,55 GHz band operating range5150—5850MHz
fop,66 GHz band operating range5945—7125MHz
PTXTX output power (MCS0, 2.4 GHz)—TBDTBDdBm
PRXRX sensitivity (MCS0)TBD——dBm
ηMax PHY throughput (single stream)—143—Mbps
Bluetooth LE 5.4
fop,BLEOperating frequency range2402—2480MHz
PTX,BLETX output power—TBDTBDdBm
PRX,BLERX sensitivity (1 Mbps)TBD——dBm

Antenna Options​

The E1M-X V2N-M1 has three antenna pads (one per band):

  1. On-module U.FL connector — connect an external antenna directly to the module.
  2. Carrier-board PCB antenna — route each ANT_* pad as a 50 Ω controlled-impedance trace to a chip / PCB antenna.
  3. Carrier-board RF connector — extend the 50 Ω trace to a U.FL / IPEX / SMA connector on the carrier.

Maximum antenna gain to maintain regulatory compliance is TBD dBi per band.

Regulatory Information​

The on-module combo radio is pre-certified for the regions below. Reusing the module's certifications on the customer's end product requires following the integration guidelines (antenna gain, RF trace, enclosure) from the certification report.

Table: Wireless Regulatory Approvals

RegionStandardCertificate IDNotes
United StatesFCC Part 15TBDModular grant pending.
EuropeRED / CETBD—
CanadaISED RSS-247TBD—
JapanMIC (Japan)TBD—

Warning: Certifications apply only when the module is used with the antenna(s) listed in the certification report. Using an unlisted antenna voids the modular grant and requires re-certification on the customer's end product.

Memories​

E1M-X offers several memory options:

  • eMMC — up to 256 GB.
  • LPDDR4X — up to 8 GB.
  • NOR Flash — on-module, boot-supported.

E1M-X V2N-M1 Memory Options (figure pending)

An optional EEPROM (N24S128C4DYT3G from onsemi) is also available on the board, connected through I2C0 on E1M-X. It can be flashed in production. I2C0 is also accessible on the E1M-X pinout. Refer to the E1M hardware design guide for details.

TPM 2.0 Module​

E1M-X V2N-M1 includes a Trusted Platform Module (TPM 2.0) for secure-boot and key-storage applications.

Real-Time Clock (RTC)​

A battery-backed real-time clock is available on-module; its 32 kHz output is exposed on RTC_CLKOUT.

PCB Temperature Sensor​

An on-board PCB temperature sensor (TI TMP112D or equivalent) is available.

Environmental & Reliability​

Operating & Storage Conditions​

Table: Environmental Conditions

ParameterSymbolMinMaxUnit
Ambient operating temperatureTA− 40+85°C
Storage temperatureTSTG− 40+125°C
Relative humidity (operating, non-condensing)RHTBDTBD%

Warning: Sustained AI workloads (DRP-AI3 + DX-M1 running concurrently) push the SoM toward its thermal envelope at +85 °C ambient. Active cooling or a copper-pour heatsink contact is recommended above ~50% DX-M1 utilisation at the high end of the temperature range.

Reflow Profile​

The E1M-X V2N-M1 is qualified per IPC/JEDEC J-STD-020 to MSL TBD. The recommended lead-free reflow profile is shown in Reflow Profile, measured on a JTR1000 convection reflow oven using ALPHA OM338 (SAC, Pb-free) solder paste. Peak package temperature is 241–244 °C. Customers must follow the reflow profile below and the dry-pack handling instructions in MSL & Handling.

E1M-X V2N-M1 Recommended Reflow Profile (Pb-free, SAC)

Table: Reflow Profile Parameters (Pb-free)

ParameterSymbolMinMaxUnit
Average ramp-up rate (TL to TP)——3°C/s
Preheat / soak time (150–217 °C)tS60120s
Time above liquidus (≥217 °C)tL4590s
Peak package temperatureTP241244°C
Average ramp-down rate (TP to TL)—− 1.6—°C/s
Time 25 °C to peak——8min

Reliability Data​

Table: Reliability Targets

ParameterSymbolValueUnit
Mean Time Between Failures (Telcordia SR-332, TA = +25 °C)MTBFTBDh
Moisture Sensitivity LevelMSLTBD—
Qualified shelf life (in dry-pack)—TBDmonths

Software & Operating System Support​

The E1M-X V2N-M1 is supported by the open-source Alp SDKTM. Out of the box, the SDK supports:

  • Bare-metal application development on the RZ/V2N's internal Cortex-M33 (200 MHz) or the on-module GD32 I/O-MCU (216 MHz).
  • Zephyr RTOS on the Cortex-M33 cores and on the Cortex-A55 cluster (SMP).
  • Linux (Yocto / buildroot BSP) on the quad Cortex-A55 application cluster, with DX-M1 driver enabled via the alp_e1m_v2m_a55 board target.

Table: Software Support Matrix

Target / RuntimeBare-metalZephyrLinuxDX-M1 driver
GD32 I/O-MCU (Cortex-M33 @ 216 MHz)YesYes——
RZ/V2N internal M33 (200 MHz)YesYes——
RZ/V2N Cortex-A55 (alp_e1m_v2n_a55)YesYesYes—
RZ/V2N Cortex-A55 (alp_e1m_v2m_a55)YesYesYesYes

Warning: Using the alp_e1m_v2n_a55 board target on a V2N-M1 module leaves the DX-M1 in reset. Always select alp_e1m_v2m_a55 to access the DX-M1.

Note: See the Alp SDKTM repository (docs/firmware-quickstart.md and docs/soms/v2n-m1.md) for the per-target build instructions. For deeper integration patterns, see AN-001 through AN-010; for DX-M1 specifically, AN-009.

Reference Schematic​

The minimum carrier-board design below brings up an E1M-X V2N-M1 with a single 5 V input, reset push-button, boot-mode DIP switch, and JTAG/SWD debug header. The DX-M1 needs no carrier-side wiring — it lives entirely on the SoM behind the on-module PCIe mux.

E1M-X V2N-M1 Minimum Reference Schematic (figure pending)

Required external components:

  • 5 V power source (≥ 5 A peak) to VDD_5V_IN (T1, T2, U1, U2, V1, V2). Size for the higher peak (DRP-AI3 + DX-M1 + dual-Ethernet) compared to a V2N-only carrier.
  • Bulk decoupling: 1 × 10 μF + 1 × 100 nF close to VDD_5V_IN.
  • Boot-mode 2-position DIP switch driving BOOT0, BOOT1 (with 10 kΩ pull-downs).
  • Reset push-button between PORn (Z1) and GND.
  • 10-pin Cortex SWD/JTAG header on JTAG_* pads (optional, for development).

Optional carrier-board components are described per interface in Interfaces, and in detail in HG-V2N-M1-001.

Compliance & Certifications​

Environmental Compliance​

Table: Environmental Compliance

StandardDescriptionStatus
RoHS 3 (EU 2015/863)Restriction of hazardous substancesCompliant
REACH (EC 1907/2006)Substances of very high concernCompliant
Halogen-free (IEC 61249-2-21)Br + Cl content limitsTBD
Conflict minerals (Dodd-Frank §1502)Tin, tungsten, tantalum, gold sourcingTBD

Wireless Certifications​

See Regulatory Information for the per-region wireless certification IDs.

Functional Safety & Industry-specific Compliance​

The E1M-X V2N-M1 is not currently certified for safety-critical applications (IEC 61508, ISO 26262, IEC 62304, etc.). Contact Alp Lab for the most recent qualification status.

Mechanical & Footprint Dimensions​

All dimensions are in mm unless otherwise noted.

Module Dimensions​

E1M-X V2N-M1 Module Top & Side View (figure pending)

Table: E1M-X V2N-M1 Mechanical Dimensions

ParameterSymbolMinMaxUnit
Module lengthL64.965.1mm
Module widthW44.945.1mm
Module height (PCB + tallest component)H—TBDmm
Module massm—TBDg

The recommended carrier-board land pattern follows IPC-7351 nominal density for LGA packages. Identical to the V2N family — V2N and V2N-M1 are pin-compatible.

E1M-X V2N-M1 Recommended Land Pattern (figure pending)

Table: Land Pattern Parameters

ParameterSymbolValueUnit
Pad pitch (signal grid)pTBDmm
Pad size (signal)—TBD × TBDmm
Pad size (GND ring)—TBD × TBDmm
Stencil material—Nano-coated steel mesh—
Stencil thickness (recommended)t80μm
Solder-mask opening—Non-solder-mask-defined—

Keep-Out Zones​

Carrier boards must keep the area directly beneath the module clear of components taller than TBD mm. RF traces (especially the three antenna feeds) must be routed away from high-current digital paths.

E1M-X V2N-M1 Keep-Out Zones (figure pending)

Module Marking​

Each module is laser-marked on the top side with:

  • Manufacturer logo (Alp Lab)
  • Full MPN (e.g. E1M-V2M101)
  • Production date code (YYWW)
  • Serial number (10 characters)
  • FCC ID, ISED IC, MIC marks (where applicable)
  • Wi-Fi MAC address (last 4 digits)
  • DX-M1 firmware version code

E1M-X V2N-M1 Module Marking Layout (figure pending)

Packaging​

Tape & Reel​

The E1M-X V2N-M1 is supplied in EIA-481-compliant carrier tape on 13" or 7" reels.

Tape & Reel Drawing (figure pending)

Table: Tape & Reel Specifications

ParameterSymbolValueUnit
Tape width—TBDmm
Pocket pitchP0TBDmm
Reel diameter (large reel)D330mm
Reel diameter (small reel)D180mm
Units per large reel—TBDpcs
Units per small reel—TBDpcs

Tray​

A JEDEC-compliant tray is available for low-volume or prototyping orders.

Tray Drawing (figure pending)

MSL & Handling​

The E1M-X V2N-M1 is classified to Moisture Sensitivity Level (MSL) TBD per IPC/JEDEC J-STD-020. Modules are shipped in dry-pack with desiccant and a humidity-indicator card.

After opening the dry-pack:

  • Floor life: TBD hours at ≤ 30 °C / ≤ 60% RH.
  • If floor life is exceeded before reflow, bake at TBD °C for TBD h before assembly.

Refer to IPC/JEDEC J-STD-033 for full moisture/reflow handling procedures.

Ordering Information​

MPN Decoder​

Table: E1M-X V2N-M1 MPN Convention

FieldExampleDescription
FamilyE1MEdge-1 AI Module standard footprint.
Form factor-VImplied 45 × 65 mm E1M-X.
Product lineV2MRenesas RZ/V2N with on-module DeepX M1 accelerator (the M in V2M denotes the M1). Sibling line V2N omits the DX-M1.
Memory tier11 = lower memory tier (32 Gbit LPDDR4X + 32 Gbit eMMC). 2 = higher tier (64 Gbit LPDDR4X + 128 Gbit eMMC).
Hardware revision01Two-digit revision; incremented on form-fit-function changes.

Note: Example: E1M-V2M101 = E1M-X form factor, RZ/V2N + DX-M1, memory tier 1, hardware rev 01.

Ordering Matrix​

Table: Ordering Information

MPNCPULPDDR4XeMMCAP coresRT coresAITemp. (°C)
E1M-V2M101R9A09G056N44GBG#AC032 GbiteMMC 5.1, 32 GbitA55 4 × 1.8 GHzV2N M33 1 × 200 MHz
I/O MCU M33 1 × 216 MHz		V2N: 4 TOPS
DeepX M1: 25 TOPS		− 40 to +85
E1M-V2M10264 GbiteMMC 5.1, 128 Gbit

All configurations above include:

  • 2.4 GHz / 5 GHz / 6 GHz Wi-Fi® + Bluetooth® 5.4 combo module
  • 2 × 1 Gbit Ethernet PHY
  • 1 × display backlight driver
  • 4 × LDOs for external cameras
  • NOR Flash (size TBD)
  • I/O MCU Cortex-M33 (216 MHz)
  • TPM (secure chip)
  • EEPROM
  • RTC
  • Temperature sensor
  • DeepX DX-M1 25-TOPS AI accelerator (PCIe-attached on-module)
  • 2 × LPDDR5X companion memory for DX-M1
  • SPI NAND companion storage for DX-M1

RoHS-compliant. Contact Alp Lab for custom assembly variants (lead finish, ball material, etc.).

References & Related Documents​

Table: Related Documents

Ref.TitleSource
[1]Renesas RZ/V2N Hardware Reference ManualRenesas Electronics
[2]Renesas RZ/V2N Series DatasheetRenesas Electronics
[3]DeepX DX-M1 Hardware Integration ManualDeepX (vendor-supplied)
[4]DeepX DX-COMTM User GuideDeepX (vendor-supplied)
[5]E1MTM SpecificationE1M-STD-1.0 / github.com/alpDevs/e1m-spec
[6]E1M-X V2N-M1 Hardware Design GuideAlp Lab (HG-V2N-M1-001)
[7]E1M-X V2N Datasheet (sibling, without DX-M1)Alp Lab (DS-V2N-001)
[8]E1M-X EVK User GuideAlp Lab (UG-E1M-X-001)
[9]E1M-X EVK Getting Started GuideAlp Lab (QS-E1M-X-EVK-001)
[10]AN-009: DeepX DX-M1 First Inference WalkthroughAlp Lab
[11]Alp SDKTM Documentationgithub.com/alpDevs/alp-sdk
[12]IPC/JEDEC J-STD-020 — Reflow ProfileJEDEC
[13]IPC/JEDEC J-STD-033 — Moisture/Reflow HandlingJEDEC

Revision History​

Table: Revision History

RevisionChangesDate
0.1Initial draft (docx port).December 2025
0.2Second draft. Added DeepX DX-M1 standalone AI accelerator description and PCIe-multiplexing details.January 2026
0.3SoM-typical sections added: Module Variants, Recommended Operating Conditions, ESD & Latch-up, Thermal Characteristics, Power Architecture / Power-Up Sequence / Power Consumption, Boot Modes (top-level), Reset & Module Enable, JTAG / SWD Debug, Wireless RF/Antenna/Regulatory subsections, Environmental & Reliability, Software & OS Support, Reference Schematic, Compliance & Certifications, Mechanical & Footprint subsections, Packaging subsections, MPN Decoder, References, Legal Notices.May 2026
0.4Pin-out drawing added: top-view, colour-coded 496-pad E1M-X diagram generated from the pin tables. On-module interface ESD/EMI protection removed except on the SDIO / SD-card interface; carrier board must now provide ESD/EMI protection on Ethernet, MIPI DSI, and MIPI CSI. Reflow profile populated (Pb-free, ALPHA OM338, peak 241–244 °C) with a parameters table. SMT stencil specified (nano-coated steel mesh, 80 μm).June 2026
0.5Cover page: replaced the block-diagram placeholder with front/back product photos of the E1M-X V2N-M1 module (with DeepX DX-M1).July 2026
0.6Cover photos swapped to transparent-background versions.July 2026

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The information in this document is provided in connection with Alp Lab AB products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document. Alp Lab reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time without notice.

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Alp Lab, Alp SDKTM, E1MTM, E1M-XTM, and the Alp Lab logo are trademarks of Alp Lab AB. Arm, Cortex, Mali, and Ethos are trademarks of Arm Limited. Renesas and RZ/V2N are trademarks of Renesas Electronics. DeepX, DX-M1, and DX-COM are trademarks of DeepX. Wi-Fi is a trademark of the Wi-Fi Alliance. Bluetooth is a trademark of the Bluetooth SIG. All other trademarks are the property of their respective owners.

Export Control​

This product may be subject to export-control regulations. The DeepX DX-M1 accelerator may be subject to additional export-control classifications beyond the base V2N silicon; consult Alp Lab and DeepX export-control guidance before re-exporting. The customer is responsible for complying with all applicable export-control laws.

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