`aen-dualcore-*` — dual M55 boot & IPC

The E8 carries two Cortex-M55 cores — HP (high-performance) and HE (high-efficiency). This family of bench examples proves both cores boot and exchange data on real silicon.

Example	What it proves	Status
`aen-hp-core-smoke`	M55-HP first light — SE releases the HP core from reset; liveness beacon in global SRAM0	PASS
`aen-dualcore-master`	Boot both cores at runtime via the SE boot service `se_service_boot_cpu(cpu_id, address)`	RESULT PASS
`aen-dualcore-probe`	Whether a dual-entry ATOC boots both cores (it boots only HP)	bench finding
`aen-dualcore-doorbell`	HE→HP MHU-1 doorbell — every ring received with both cores live	PASS
`aen-dualcore-ipc`	Bidirectional HE↔HP shared-memory request/response, 64/64 round-trips	RESULT PASS

Source: examples/aen/.

How it works

Boot. The SES-booted core starts the other M55 at runtime over the seservice0 MHU. (Dual-entry ATOC was found to boot only HP — hence the runtime boot path.)
Doorbell. Cores signal each other through the ARM MHU-1 windows (sender 0x400B0000, receiver 0x400A0000).
Data. A {seq, len, payload} mailbox lives in global SRAM0; correctness handshakes on seq, not the doorbell edge. CONFIG_DCACHE=n is mandatory — the shared mailbox is off-cache.

For the portable framed-RPC surface on top of this, see aen-rpc-pingpong.

`board.yaml`

Both peer images ship; the dual-core build targets the HP and HE cores:

som:
  sku: E1M-AEN801

preset: e1m-evk

cores:
  m55_hp:
    app: ./src/hp
  m55_he:
    app: ./src/he

diagnostics:
  log_level: info

Expected output

[dualcore-ipc] HP up, HE up
[dualcore-ipc] round-trips: 64/64
[dualcore-ipc] RESULT PASS

How it works​

board.yaml​

Expected output​

See also​

How it works

`board.yaml`

Expected output

See also