v2n-gd32-bridge-hil-soak

Pass/fail soak of the whole GD32 bridge command set over the 25 MHz SPI fast path. Where v2n-gd32-bridge-ping proves the link, this proves the opcodes: every command the bridge firmware implements round-trips each cycle with a self-contained verification — no external instruments needed.

Source: examples/v2n/v2n-gd32-bridge-hil-soak/.

What it exercises per cycle

Test	Opcodes	Self-verification
ping / get_version / get_build_id / reset_reason	0x00–0x03	status OK, version matches init, build-id constant, cause in-range
gpio	0x10/0x11	full-mask read OK; mask=0 write (provable no-op)
pwm set/get + single-pulse + capture	0x20–0x26	1 kHz / 25 % readback within 1 %; parked at 0 % after
adc read + stream	0x30, 0x33–0x35	4 samples ≤ VREF; > 0 stream samples after 50 ms @ 1 kHz (the stream-DMA regression test)
dac	0x50/0x51	1650 mV readback ± 16 mV; parked at 0 after
qenc / counter	0x60/0x61, 0x70	reset → position exactly 0; counter strictly increasing
trng / tmu	0x80, 0x90	two 16-byte pulls non-constant + distinct; sqrt(4)=2, sin(0)=0 within 1e-3
timer_sync / power_mode	0x27/0x28	link TIMER0→TIMER7 then unlink; mode 0 ("run") no-op
da9292 sentinel	0x40	must answer 0xFF — no DA9292 net reaches the GD32 on this HW rev
ota_get_state	0xF5	NOSUPPORT on an unarmed build, or a sane state snapshot

Verification checks are self-contained: readback compares (PWM, DAC), range sanity (ADC, reset-reason), monotonicity (counter), entropy (TRNG), exact math (TMU), and documented-sentinel asserts. Instrument-grade checks (scope on PWM, precision source on ADC) remain separate HIL-plan rows.

The soak is silicon-validated — the v0.6.0 release recorded a 253/253 clean bench run on firmware v0.2.8/v0.2.9.

See also

• GD32 Bridge Ping — link-level liveness
• GD32 bridge protocol — wire spec