v2n-gd32-swd-flash

Host-driven SWD bit-bang to the on-module GD32G553 over three GPIOs (SWDIO + SWCLK + optional NRST). Attaches from the Renesas RZ/V2N host, reads SW-DP IDCODE, halts the Cortex-M33, erases a flash sector, writes + verifies a scratch pattern, and releases the core.

This is the recovery / first-flash path for the on-module bridge — works even when the application-bootloader OTA path is unreachable (corrupt bridge image, factory first-flash, dev-board bring-up). No external probe required.

Three ways to flash the bridge

Path	Tooling	When
External SWD probe (swd_probe backend)	west alp-flash → SEGGER J-Link (-device GD32G553MEY7TR, requires J-Link software ≥ V9.46); OpenOCD / pyOCD fallbacks for CMSIS-DAP / ST-Link	Bench / production flashing — the primary path.
OTA Path-A (over the bridge itself)	OTA_BEGIN → OTA_WRITE_CHUNK → OTA_VERIFY (SHA-256) → OTA_COMMIT, A/B slots with rollback	In-field firmware update of a working bridge.
Host SWD bit-bang (this example)	Three Renesas GPIOs, no probe	Recovery when the bridge image is corrupt and no probe is attached.

Source: examples/v2n/v2n-gd32-swd-flash/.

What it shows

1. Opening three alp_gpio_t handles for SWDIO, SWCLK, NRST.
2. gd32_swd_init configures SWDIO + SWCLK as outputs at the SWD idle state.
3. gd32_swd_connect line-resets the link, performs the JTAG-to-SWD switch sequence, reads DPIDR. Logs whether the IDCODE matches the expected 0x6BA02477 (Cortex-M33 r0p1 SW-DPv2 — the GD32G553's documented value).
4. gd32_swd_halt puts the Cortex-M33 into debug-halt via DHCSR DBGKEY + C_HALT.
5. gd32_swd_flash_erase erases the enclosing 2 KiB sector.
6. gd32_swd_flash_write programs a 64-byte ramp pattern.
7. gd32_swd_flash_verify reads it back via AHB-AP memory reads.
8. gd32_swd_reset_and_run releases the core via HW NRST pulse (when wired) or AIRCR.SYSRESETREQ otherwise.

board.yaml

som:
  sku: E1M-V2N101

preset: e1m-x-evk

cores:
  a55_cluster:
    os: "off"              # A55 cluster intentionally off — M33-SM is the SWD host
  m33_sm:
    # os: omitted → topology default (m33_sm → zephyr).
    app: ./src
    peripherals: [gpio]

chips:
  - gd32_swd

diagnostics:
  log_level: info

SWD pin model — host-side SWD (2026-05 hardware decision)

GD32 in-field reflash uses SWD-from-host, not factory-ISP / BOOT0. The earlier "BOOT0 → Renesas P75" plan was dropped in favour of a software SWD bit-bang from the Renesas host — SWD works regardless of GD32 firmware state, where factory-ISP would depend on the GD32 boot ROM staying intact.

Canonical pad assignments on V2N (maintainer-confirmed):

Signal	Renesas pad	Notes
GD32_SWDIO	P70	Was GPT0_GTIOC0A.
GD32_SWCLK	P71	Was GPT0_GTIOC0B.
GD32_NRST	P74	Was E1M PWM4 / GPT4_GTIOC4A. Shared with the primary PMIC reset out — host pad must be configured open-drain (drive low to assert reset; HiZ to release). External pull-up returns the line to its released state.

P75 becomes unassigned on the Renesas side (BOOT0 dropped, PWM5 moved entirely to GD32 — see PWM Fan Control).

See also

• <alp/chips/gd32_swd.h>
• GD32 bridge protocol §10 Path B
• Tutorial 7 — recovering a bricked bridge