<alp/pwm.h> — Pulse-Width Modulation

PWM channels for LED control, motor drive, servo pulses, fan control, audio prototyping, etc.

Header

#include <alp/pwm.h>
#include <alp/e1m_pinout.h>

Quick example

alp_pwm_t *pwm = alp_pwm_open(&(alp_pwm_config_t){
    .channel_id = ALP_E1M_PWM0,
    .period_ns  = 1000000u,            // 1 kHz
    .polarity   = ALP_PWM_POLARITY_NORMAL,
});
if (pwm == NULL) return alp_last_error();

alp_pwm_set_duty(pwm, 500000u);        // 50 % (500 µs of the 1 ms period)

alp_pwm_close(pwm);

Config struct

Field	Type	Notes
channel_id	uint32_t	ALP_E1M_PWM0 … ALP_E1M_PWM7. Must be < ALP_E1M_PWM_COUNT.
period_ns	uint32_t	PWM period in nanoseconds. 0 = devicetree default.
polarity	alp_pwm_polarity_t	ALP_PWM_POLARITY_NORMAL / ALP_PWM_POLARITY_INVERTED.

Operations

Function	Description
alp_pwm_set_duty(pwm, pulse_ns)	Set the active-level pulse width (≤ period; 0 = fully off, period = fully on).
alp_pwm_set_period(pwm, period_ns)	Update the period. Duty is reset to 0 % — re-arm with alp_pwm_set_duty.
alp_pwm_configure(pwm, align_mode, dead_time_ns, break_cfg)	Sticky per-channel tuning: alignment mode, dead-time, break input.
alp_pwm_close(pwm)	Drive the output low and release the handle.

v0.5 extras

alp_pwm_capture_t adds input-capture support, and alp_pwm_single_pulse() emits a one-shot pulse without leaving the channel running.

V2N: GD32-side PWM

On the E1M-X V2N family, the eight cross-edge PWM channels are owned by the on-module GD32G553 supervisor MCU, not the Renesas SoC. The host driver routes alp_pwm_* calls through the GD32 bridge protocol:

gd32g553_t bridge;
gd32g553_init(&bridge, spi, brd_i2c, GD32G553_BRIDGE_DEFAULT_I2C_ADDR);
gd32g553_pwm_set(&bridge, /* channel */ 0u, 1000000u, 500000u);

The pwm-led-fade and v2n-pwm-fan-control examples demonstrate both paths.

See also

• Examples: pwm-led-fade
• <alp/peripheral.h>