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Carrier Board Design Guide

This guide provides recommendations for designing custom carrier boards that interface with Alp Lab E1M and E1M-X modules. The standard's authoritative mechanical and electrical clauses live in alplabai/e1m-spec/STANDARD.md; the notes below are practical guidance for board designers.

Overview​

E1M modules are designed as system-on-module (SoM) products that plug into application-specific carrier boards. The carrier provides:

  • Power regulation and distribution
  • Physical connectors (USB, Ethernet, camera, display)
  • Application-specific circuitry (sensor interfaces, motor drivers, displays, …)
  • Mechanical mounting and enclosure integration

Reference design: the Alp Lab EVKs​

The two stock EVK presets — E1M EVK (35 × 35) and E1M-X EVK (45 × 65) — are the canonical reference designs. Most production carriers inherit ~80 % of the EVK's chip population. Two ways to consume the reference:

  • Reference + override — declare carrier.name: E1M-EVK in board.yaml and list only the deltas under populated:.
  • Fork the carrier preset — copy metadata/carriers/e1m-evk.yaml to my-board.yaml, edit, and reference it.

Either way, the SDK's loader compiles only the chip drivers your carrier actually populates.

E1M module placement​

The LGA footprint, land pattern, and keepout zones are normative in the spec. Mechanical drawings, STEP files, and footprint TSVs live under alplabai/e1m-spec/images and source/.

Keepout zones​

Maintain the following clearances around the E1M module footprint:

  • Above the module — clearance for module height (5 mm minimum)
  • Around the module — clearance for rework and inspection
  • Bottom-side keepout — do not place components or pour copper under the SoM beyond what the spec authorises

Mounting​

E1M and E1M-X are soldered to the carrier via the LGA pads. No separate mating connector is required. Mounting holes (where present in the spec) are advisory for mechanical stiffening.

Power supply design​

Input power​

RailVoltageNotes
VIN3.3 V or 5 V (per SoM datasheet)Main module power supply. Generated internally to all required rails by on-module PMICs.
V3V33.3 V outputAvailable for low-current carrier-side loads.
V1V81.8 V outputI/O reference for level-translated carrier signals.

Per-SoM peak / steady current and PMIC sequencing details are in the SoM's datasheet (request from Alp Lab).

Decoupling​

Place bulk and high-frequency decoupling close to the SoM power pads:

  • Bulk — 100 µF electrolytic or polymer per power rail
  • High-frequency — 100 nF + 1 µF MLCC per power-pad group

Power sequencing​

The SoM handles internal sequencing autonomously through its on-module PMIC(s). Carriers only need to drive VIN and observe MODULE_EN / RESET# per the spec.

Signal routing​

High-speed signals (E1M-X)​

For MIPI CSI-2, MIPI DSI, USB 3.0, PCIe, and Ethernet:

  • Route as differential pairs with controlled impedance (typically 100 Ω differential)
  • Minimise stub lengths
  • Length-match within differential pairs to ≤ 0.1 mm
  • Use ground-referenced stripline or microstrip
  • Reference plane continuity is critical — avoid splits under high-speed pairs

SPI / I²C / UART​

Standard digital interfaces can be routed as single-ended traces:

  • Keep trace lengths under 150 mm where possible
  • Add series termination resistors (22–33 Ω) on SPI clock lines if needed
  • Pull-up resistors for I²C: 2.2 kΩ to 4.7 kΩ to V3V3 (or V1V8 if the bus is referenced to 1.8 V)

GPIO​

  • Default GPIO output drive strength is configurable through the SDK at *_open time
  • For high-current loads, use external buffers or MOSFETs

ESD protection​

External-facing connectors (USB, Ethernet, GPIO breakouts) require ESD protection diodes. Choose parts with capacitance compatible with the signal class (low-cap parts for USB 3.0 and Ethernet; standard TVS for GPIO).

Thermal management​

Higher-performance modules (V2N, V2N-M1) benefit from a carrier-side thermal interface:

  • A copper pour under the module connected to GND vias acts as a heat spreader
  • Heatsink mounting is recommended for sustained inference workloads
  • See the per-SoM thermal characterisation in the SoM datasheet

Design review checklist​

Before sending your carrier to fabrication:

  • LGA footprint matches the spec's land pattern (E1M or E1M-X as appropriate)
  • All power rails are present and properly decoupled
  • MODULE_EN and RESET# are wired according to the spec
  • High-speed differential pairs are impedance-controlled and length-matched
  • Keepout zones around the SoM are respected
  • ESD protection is present on all external-facing connectors
  • Thermal management is adequate for the target workload
  • A board.yaml carrier preset is authored and validated with validate_board_yaml.py

Resources​

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