E1M-AEN

The E1M-AEN is an edge AI System-on-Module built around the Alif Semiconductor Ensemble family of processors. AEN modules ship in the 35 × 35 mm E1M form factor and target ultra-low-power inference at the edge.

Module variants

All AEN SKUs share the same module PCB. Pick by Alif silicon tier (cores + NPU count + memory).

SKU	Silicon	Status
E1M-AEN301	Alif Ensemble E3	production
E1M-AEN401	Alif Ensemble E4	preliminary
E1M-AEN501	Alif Ensemble E5	preliminary
E1M-AEN601	Alif Ensemble E6	preliminary
E1M-AEN701	Alif Ensemble E7	production
E1M-AEN801	Alif Ensemble E8	preliminary

At a glance

Parameter	Value
Application core	Arm Cortex-M55 HP @ 400 MHz + Cortex-M55 HE @ 160 MHz
Real-time core	Cortex-A32 @ 800 MHz (E5/E6/E7/E8 variants)
AI accelerators	2× Arm Ethos-U55 (all SKUs) + 1× Arm Ethos-U85 (E4/E6/E8 only) — Transformer-capable, generative-AI forward path
AI throughput	up to ~1024 GOPS (U55 path); U85 adds Transformer kernels
Power profile	Ultra-low-power
Form factor	E1M (35 × 35 mm), LGA
OS targets	Zephyr · bare-metal

What's on the module

Role	Part	Bus / signal	Driver
Application SoC	Alif Ensemble E3..E8	--	(vendor HAL)
Wi-Fi 6 + BLE 5.4	TI CC3501E	inter-chip SPI1 + SDIO	<alp/chips/cc3501e.h>
Secure element	Infineon OPTIGA Trust M	LPI2C	<alp/chips/optiga_trust_m.h>
RTC	Micro Crystal RV-3028-C7	LPI2C	<alp/chips/rv3028c7.h>
Temperature sensor	TI TMP112	LPI2C	<alp/chips/tmp112.h>
EEPROM (SoM manifest)	Onsemi N24S128	LPI2C	<alp/chips/eeprom_24c128.h>
Ethernet PHY	TI DP83825IRMQR	RMII	Zephyr PHY driver

CC3501E coprocessor

Wi-Fi 6 and BLE 5.4 ride a dedicated TI CC3501E co-MCU rather than driver-level Wi-Fi on the Alif silicon. The Alif is master; the host driver speaks the documented inter-chip protocol over SPI (default) or SDIO (optional, higher throughput). SDIO shares the Alif's single SDIO controller with the micro-SD slot, so it is mutually exclusive with an SD card.

The bridge firmware is embedded in the SDK at firmware/cc3501e/ (modeled on the GD32 bridge, not a separate repo). In v0.8.0 it is silicon-validated on the E1M-AEN801 (Alif E8): beyond the v0.1 META group (PING / GET_VERSION / GET_MAC / RESET), real-silicon Wi-Fi scan (with security decode), Wi-Fi STA connect, BLE scan (ble_gap_disc), and the GPIO proxy all pass on the bench. Wi-Fi and BLE are not yet concurrent — a conf-gated limitation (shared HIF), not a code limit.

The validated AEN rev (FIB v0.0.207) wires the SPI link with a hardware SS0 chip-select (Alif P14_7 = SPI1_SS0_C) and per-phase READY gating — not the CS-less 3-wire framing the firmware also supports.

alp_spi_t *bus = alp_spi_open(&(alp_spi_config_t){
    .bus_id        = ALP_E1M_SPI1,
    .freq_hz       = 8000000,
    .mode          = ALP_SPI_MODE_0,
    .bits_per_word = 8,
});

cc3501e_t fw;
cc3501e_init(&fw, bus);
cc3501e_reset(&fw);

The full bridge protocol (defined in <alp/protocol/cc3501e.h>) covers Wi-Fi (scan / STA / AP / RSSI / IPv4), BLE (GAP + GATT), a GPIO proxy (configure / read / write / edge-interrupt CC3501E pins, plus the two camera-LDO enables), a coarse power-policy hint, and OTA-over-bridge firmware update (PSA-FWU streaming, RAM-stage + flash-window recovery). On real E8 silicon the GPIO proxy is bench-validated (pass=8 / fail=0) and OTA-over-bridge delivers reliable streaming. The host chip driver header is <alp/chips/cc3501e.h>; see the aen-cc3501e-bringup example.

Inference

AEN's NPUs are exposed through the SDK's <alp/inference.h> dispatcher. The TFLite-Micro library picks the right backend per SKU:

SKU	Primary NPU	Kconfig
AEN301 / AEN501 / AEN701 (E3 / E5 / E7)	2× Ethos-U55	CONFIG_ALP_TFLM_ETHOS_U55=y
AEN401 / AEN601 / AEN801 (E4 / E6 / E8)	1× Ethos-U85 (primary) + 2× Ethos-U55 (secondary)	CONFIG_ALP_TFLM_ETHOS_U85=y + CONFIG_ALP_TFLM_ETHOS_U55=y

Models are Vela-compiled TFLite Micro programs. The SDK ships a complete reference at examples/aen/edgeai-vision-aen (camera → ISP → Ethos-U inference → OLED overlay).

On the E8 the NPU complex is 1× Ethos-U85 (256-MAC) + 2× Ethos-U55 (three accelerators, two devicetree nodes). Real person_detect MobileNet inference (int8, 100 % NPU) runs to completion on the U85 with the model resident in MRAM — bench-validated, see aen-npu-inference. Any DMA-master block on the E8 M55 (the NPU, GMAC, SDHC) must keep its DMA-visible buffers in global SRAM0/SRAM1 with CONFIG_DCACHE=n — never the M55 DTCM, which is off the DMA bus.

E1M-AEN801 (Alif E8) bench status

v0.7 is the first full on-silicon bring-up of the E1M-AEN801 (Alif Ensemble E8). The default burn path is Flow D — J-Link direct MRAM flash, which activates with the part-number device profile AE822FA0E5597LS0_M55_HE (not the generic Cortex-M55 profile) and needs the J-Link V9.46+ DLL.

15 of 17 aen-* apps PASS on real silicon:

Status	Peripherals
✅ PASS	GPIO, UART, PWM (UTIMER), SPI, Counter, I²C + EEPROM (24C128), Watchdog (CMSDK), ADC, DAC, Ethernet (GMAC), Ethos-U85 + Ethos-U55 NPU inference, PDM mics (live PCM), I²S TX, CRC / DMA (PL330) / HWSEM / LPTIMER / LPRTC regchecks
🟡 PARTIAL (hardware-gated)	Quadrature encoder (driver reads clean; count static until the encoder is spun), SD card (DWC SDHC inits; card unreachable until the EVK SDIO mux is set)

Highlights:

• Ethernet is BENCH-VERIFIED — DHCP lease acquired, server-side REACHABLE. The fix was placing the GMAC DMA descriptor rings + net_buf pool in global SRAM0 (zephyr,sram = &sram0), not the M55 DTCM, with CONFIG_DCACHE=n.
• Analog — DAC and ADC bench-confirmed with corrected references (DAC 0.750 V, ADC 1.8 V) via a DAC0 → ADC loopback.
• Dual-core — both M55 cores (HE + HP) boot via the SE runtime boot service; HE↔HP IPC works over ARM MHUv2 (alif,mhuv2-mbox): shared-memory round-trips, MHU-1 doorbell, and OpenAMP RPMsg pingpong all PASS.
• Security — SE-CryptoCell AES / SHA / AEAD compute is default-ON and bench-validated; the portable <alp/security.h> PSA surface routes to the hardware accelerator transparently.

See the AEN examples for the per-peripheral bench apps.

AEN401 / AEN601 board wrappers (pre-silicon)

The E1M-AEN801 (Alif E8) is the silicon-validated member of the family. v0.9.0 adds two more Zephyr board wrappers — for the E4 and E6 Ensemble tiers — that build against real Alif device-tree sources but have not yet been on a bench. They are compile-verified and pre-silicon: each produces a real zephyr.bin, but live bring-up is gated until hardware is in hand.

SKU / silicon	Board target	State
E1M-AEN401 — Alif Ensemble E4 (AE402FA0E5597LE0)	alp_e1m_aen401_m55_hp/ae402fa0e5597le0/rtss_hp	Compile-verified, bench-gated
E1M-AEN601 — Alif Ensemble E6 (AE612FA0E5597LS0)	alp_e1m_aen601_m55_hp/ae612fa0e5597ls0/rtss_hp	Compile-verified, bench-gated

Both mirror the AEN801 M55-HP baseline: the E1M-EVK debug console on Alif UART5 (P3_4 / P3_5), the on-die MRAM flash controller, and an MCUboot-compatible 5632 KiB partition map (64 KiB mcuboot + two 2688 KiB image slots + scratch + storage).

• AEN401 (E4) — 2× Cortex-M55 + 2× Ethos-U55 + 1× Ethos-U85 (no Cortex-A32 / Linux core). Beyond the baseline it wires a USB host controller node (xHCI USB-2.0 dual-role, alif,xhci-uhc) for USB-host workloads (see <alp/usb.h>).
• AEN601 (E6) — carries an A32 alongside the M55 pair, but this wrapper is the M55-HP subsystem only; the A32/Linux core is out of scope for the Zephyr baseline. It boots console + storage from on-die MRAM; the on-module buses (GPIO / I²C / SPI / Ethernet / USB) and inter-core IPC are added once grounded and benched on E6 silicon.

Treat these as engineering pre-enablement, not production targets — only the AEN801 (E8) has passed on-silicon bring-up. The E3/E5/E7 (AEN301/AEN501/AEN701) tiers ship as production silicon but do not yet carry a dedicated AEN board wrapper in the SDK.

Debug console

The E1M-AEN SoM (Altium rev 2626-R2) routes the dedicated debug-console UART on two E1M pads previously marked RSVD, mirroring the E1M-X mapping:

E1M pad	Signal
AD3	DBG_TX
AE3	DBG_RX

Each pad keeps a GPIO alternate function, identical to the E1M-X DBG pads.

Boot + identification

AEN follows the standard two-stage SoM-ID flow used by every Alp Lab module family:

1. EEPROM manifest — 128-byte block on the on-module 24C128 EEPROM carrying family / SKU / hw_rev / serial / mfg date. Read via alp_hw_info_read().
2. BOARD_ID ADC — per-rev resistor divider sampled by the SDK at boot to confirm the running firmware matches the hardware revision.

See <alp/hw_info.h>.

Getting started

1. Mount the E1M-AEN on a compatible board (E1M-EVK or custom) using the E1M LGA pads.
2. Install the Alp SDK.
3. Drop a board.yaml at your app root with som.sku: E1M-AEN701 (or your SKU) and preset: e1m-evk.
4. Build and flash with west alp-build -b alp_e1m_evk_aen .... See the Quick Start.

Documents

• E1M-AEN Datasheet — DS-AEN-001

Resources

• Firmware quickstart — AEN-specific patterns
• <alp/inference.h> — Ethos-U dispatcher
• Chip catalogue — every on-module driver
• Industrial inquiries