E1M-X V2N-M1
The E1M-X V2N-M1 combines the Renesas RZ/V2N processor with the DeepX M1 NPU to deliver 25 TOPS of dense inference performance in a single Edge AI module.
Overview
| Parameter | Value |
|---|---|
| Application Core | Quad Arm Cortex-A55 @ 1.8 GHz (RZ/V2N) |
| Real-Time Core | Arm Cortex-M33 (RZ/V2N) |
| AI Accelerator 1 | Renesas DRP-AI3 (4 TOPS dense) |
| AI Accelerator 2 | DeepX M1 (21 TOPS dense) |
| Total AI Performance | 25 TOPS (dense) |
| Module Dimensions | 65 x 45 x 5 mm |
| Form Factor | E1M SODIMM |
| Price | $179 |
Key Features
- 25 TOPS combined AI performance from dual accelerators (DRP-AI3 + DeepX M1)
- Quad Cortex-A55 @ 1.8 GHz running a full Linux distribution
- Cortex-M33 real-time subsystem for deterministic sensor and actuator control
- Same 65 x 45 x 5 mm form factor as the E1M-X V2N for drop-in upgrades
- Pin-compatible E1M SODIMM connector
Dual Accelerator Architecture
The V2N-M1 is unique in combining two independent inference engines:
| Accelerator | Performance | Strengths |
|---|---|---|
| DRP-AI3 | 4 TOPS dense | Low-latency, tightly coupled to ISP |
| DeepX M1 | 21 TOPS dense | High-throughput, large model support |
This allows workloads to be partitioned across both accelerators. For example, a vision pipeline can run a lightweight detection model on the DRP-AI3 while a heavier classification or segmentation model runs on the DeepX M1.
Block Diagram
Upgrading from V2N
The E1M-X V2N-M1 shares the same SODIMM pinout and physical dimensions as the base E1M-X V2N. Existing carrier board designs work without modification. The only change required is a software update to enable the DeepX M1 accelerator.
Getting Started
- Connect the E1M-X V2N-M1 to a compatible carrier board via the SODIMM connector.
- Flash the Linux BSP with DeepX M1 driver support.
- Install the ALP SDK for Cortex-M33 development.
- Deploy models to both accelerators using the provided toolchain.