E1M-X V2N

The E1M-X V2N is a high-performance edge AI System-on-Module powered by Renesas RZ/V2N, combining quad Cortex-A55 application cores with a dedicated DRP-AI3 accelerator for real-time vision and inference workloads. It ships in the 45 × 65 mm E1M-X form factor.

Module variants

Both SKUs share the same silicon + PCB. Pick by memory budget.

SKU	Memory	Status
E1M-V2N101	32 Gbit LPDDR4X + 32 Gbit eMMC	production
E1M-V2N102	64 Gbit LPDDR4X + 64 Gbit eMMC	production

At a glance

Parameter	Value
Application core	Quad Arm Cortex-A55 @ 1.8 GHz
Real-time core	Arm Cortex-M33
AI accelerator	Renesas DRP-AI3
AI performance	4 TOPS (dense)
Module dimensions	65 × 45 × 5 mm
Form factor	E1M-X (45 × 65 mm), LGA
OS targets	Yocto Linux (A55) · Zephyr / bare-metal (M33)
Indicative price	$89

What's on the module

Role	Part	Bus / signal	Driver
Application SoC	Renesas RZ/V2N (R9A09G056N44)	--	(vendor HAL)
Companion supervisor MCU	GigaDevice GD32G553MEY7TR	SPI + I2C bridge	<alp/chips/gd32g553.h>
Primary PMIC	Qorvo ACT88760-120.E1	I2C 0x25/0x26	<alp/chips/act8760.h>
Secondary PMIC	Renesas DA9292	I2C 0x1E	<alp/chips/da9292.h>
Clock generator	Renesas / IDT 5L35023B	I2C 0x68	<alp/chips/clk_5l35023b.h>
RTC	Micro Crystal RV-3028-C7	I2C 0x52	<alp/chips/rv3028c7.h>
Temperature sensor	TI TMP112	I2C 0x40	<alp/chips/tmp112.h>
Secure element	Infineon OPTIGA Trust M	I2C 0x30	<alp/chips/optiga_trust_m.h>
EEPROM (SoM manifest)	Onsemi N24S128	I2C 0x50	<alp/chips/eeprom_24c128.h>
Wi-Fi 6 + BLE 5.4	Murata LBEE5HY2FY-922	SDIO + UART + I2S	<alp/chips/murata_lbee5hy2fy.h>
Ethernet PHY ×2	Realtek RTL8211FDI	RGMII + MDIO	<alp/chips/rtl8211fdi.h>
eMMC	(variant per SKU)	Renesas SD0	Zephyr SD subsystem
NOR flash	(variant per SKU)	Renesas xSPI0	Zephyr flash subsystem

Processor architecture

Application cores (Cortex-A55)

Four Cortex-A55 cores running at up to 1.8 GHz host a full Linux distribution (Yocto-built). They handle application logic, networking, display output, and pre/post-processing for AI pipelines.

Real-time core (Cortex-M33)

The Cortex-M33 subsystem operates independently and runs bare-metal or Zephyr firmware via the ALP SDK. It is ideal for:

• Sensor data acquisition with deterministic latency
• PWM and motor control
• Safety-critical tasks

DRP-AI3 accelerator

Renesas's DRP-AI3 provides 4 TOPS of dense inference performance. Models are deployed through the SDK's <alp/inference.h> dispatcher with the ALP_SDK_INFERENCE_DRPAI Kconfig. Model conversion uses the upstream DRP-AI Translator toolchain.

GD32 supervisor MCU

The V2N module's GD32G553 supervisor MCU owns all eight E1M PWM channels (PWM0..PWM7 on GD32 PA11 / PB1 / PB14 / PC5 / PC10 / PC11 / PC12 / PD0), the dual ADC/DAC bank, the Wi-Fi/BT REG_ON pins, the OPTIGA reset, and 18 IO routes to the E1M edge.

2026-05 hardware decision: GD32-only PWMs. The earlier "either GD32 or Renesas, picked SoM-wide via resistor strap" cross-source design was dropped — Renesas drives no PWMs on V2N. The GPT13_GTIOC13A/B (P64/P65) and GPT4_GTIOC4B (P75) rows that previously appeared in the Renesas peripheral map were removed. The resistor-strap selection is no longer applicable; there's nothing to switch between.

The host driver speaks both transports:

• SPI fast path — Renesas RSPI master ↔ GD32 slave. Use for high-frequency telemetry and PWM updates.
• I2C management path — on BRD_I2C, GD32 at 7-bit 0x70. Use when you're already on BRD_I2C for the PMIC fleet.

gd32g553_t bridge;
gd32g553_init(&bridge, spi, brd_i2c, GD32G553_BRIDGE_DEFAULT_I2C_ADDR);

uint32_t period_ns = 1000000u; // 1 kHz
uint32_t duty_ns   = 500000u;  // 50 %
gd32g553_pwm_set(&bridge, /* channel */ 0u, period_ns, duty_ns);

The wire protocol and bring-up flow are documented in the SDK repo at docs/gd32-bridge-protocol.md.

Dual Ethernet

Two RTL8211FDI gigabit PHYs sit on separate MDIO buses. The SDK's PHY driver takes function-pointer callbacks so it works against any MDIO controller, including bridge-side MDIO:

rtl8211fdi_t phy0;
rtl8211fdi_init(&phy0, /* phy_addr */ 0,
                my_mdio_read, my_mdio_write, mdio_dev);
rtl8211fdi_soft_reset(&phy0, 500000);
rtl8211fdi_restart_autoneg(&phy0);

Getting started

1. Mount the E1M-X V2N on a compatible carrier (E1M-X-EVK or custom).
2. Flash the Yocto image to the A55 cluster (MACHINE = e1m-v2n101-a55).
3. For M33 development, install the ALP SDK and drop a board.yaml v2 with som.sku: E1M-V2N101 and a cores.m33_sm: block — or pick one of the heterogeneous flagship examples that drives both halves from one file.
4. Build with west alp-build alp-sdk/examples/rpmsg-v2n (heterogeneous) or west alp-build -b alp_e1m_v2n101_m33_sm alp-sdk/examples/v2n/v2n-gd32-bridge-ping (M33-only).

Resources

• Firmware quickstart — V2N-specific patterns
• <alp/inference.h> — DRP-AI3 dispatcher
• Chip catalogue — every on-module driver
• E1M-X EVK — reference carrier
• Industrial inquiries